Texas Instruments TMS3320C5515 1.7.6 EMIF and USB Byte Access

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System Configuration and Control

Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued)

Bit Field Value Description

5 PG3_RST Peripheralgroup 3 software reset bit. Drives the MMC/SD0, MMC/SD1, I2S0, and I2S1 reset signal.

Write0 Writingzero has no effect

Write1 Writingone starts resetting the peripheral group

Read0 Readingzero means that peripheral group is out of reset

Read1 Readingone means the peripheral group is being held in reset and should not be accessed

4 DMA_RST DMAsoftware reset bit. Drives the reset signal to all four controllers.

Write0 Writingzero has no effect

Write1 Writingone starts resetting the peripheral group

Read0 Readingzero means that peripheral group is out of reset

Read1 Readingone means the peripheral group is being held in reset and should not be accessed

3 USB_RST USBsoftware reset bit. Drives the USB reset signal.

Write0 Writingzero has no effect

Write1 Writingone starts resetting the peripheral group

Read0 Readingzero means that peripheral group is out of reset

Read1 Readingone means the peripheral group is being held in reset and should not be accessed

2 SAR_RST SARsoftware reset bit and reset for most analog-related register in the IO-space address range of

0x7000-0x70FF

Write0 Writingzero has no effect

Write1 Writingone starts resetting the peripheral group

Read0 Readingzero means that peripheral group is out of reset

Read1 Readingone means the peripheral group is being held in reset and should not be accessed

1 PG1_RST Peripheralgroup 1 software reset bit. Drives the EMIF and all three timer reset signal.

Write0 Writingzero has no effect

Write1 Writingone starts resetting the peripheral group

Read0 Readingzero means that peripheral group is out of reset

Read1 Readingone means the peripheral group is being held in reset and should not be accessed

0 I2C_RST I2Csoftware reset bit. Drives the I2C reset signal.

Write0 Writingzero has no effect

Write1 Writingone starts resetting the peripheral group

Read0 Readingzero means that peripheral group is out of reset

Read1 Readingone means the peripheral group is being held in reset and should not be accessed

1.7.6 EMIF and USB Byte Access

The C55x CPU architecture cannot generate 8-bit accesses to its data or I/O space. But in some cases

specific to the USB and EMIF peripherals, it is necessary to access a single byte of data. For example,

when writing byte commands to NAND Flash devices.

For these situations, the upper or lower byte of a CPU word access can be masked using the BYTEMODE

bits of the EMIF system control register (ESCR) and the USB system control register (USBSCR). The

BYTEMODE bits of ESCR only affect accesses to the external memory and the EMIF registers. The

BYTEMODE bits of USBSCR only affect CPU accesses to the USB registers. Table 1-60 and Table 1-61

summarize the effect of the BYTEMODE bits for different CPU operations.

NOTE: The BYTEMODE bits of the EMIF system control register should only be used for controlling

CPU accesses to NAND Flash devices and EMIF registers.

75

SPRUFX5A–October 2010 –Revised November 2010 SystemControl

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Contents

Main Page Contents Page Page Page Page Page Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Page Page Page Chapter 1 System Control 1.1 Introduction 1.1.1 BlockDiagram 1.1.2 CPU Core 1.1.3 FFT Hardware Accelerator 1.1.4 Power Management 1.1.5 Peripherals 1.2 System Memory 1.2.1 Program/DataMemory Map System Memory Figure 1-2. DSP Memory Map System Memory Table 1-2. DARAM Blocks (continued) Page 1.2.2 I/O Memory Map 1.3 Device Clocking 1.3.1 Overview Page Device Clocking www.ti.com Copyright 2010, Texas Instruments Incorporated Figure 1-3. DSP Clocking Diagram 22 SystemControl SPRUFX5AOctober 2010 Revised November 2010 SubmitDocumentation Feedback 1.3.2 Clock Domains 1.4 System Clock Generator 1.4.1 Overview ( ) 1.4.2 Functional Description Page 1.4.3 Configuration Page Page 1.4.4 Clock Generator Registers Page Page System Clock Generator Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions 1.5 Power Management 1.5.1 Overview 1.5.2 Power Domains Table 1-20. DSP Power Domains 1.5.3 Clock Management Page Figure 1-12. Idle Configuration Register (ICR) [0001h] Table 1-21. Idle Configuration Register (ICR) Field Descriptions Page Page Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued) Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions Page Page Page Page 1.5.4 Static Power Management Table 1-28. RTC Power Management Register (RTCPMGT) Field Descriptions Table 1-29. RTC Interrupt Flag Register (RTCINTFL) Field Descriptions Page Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A] Figure 1-22. RAM Sleep Mode Control Register3 [0x1C2B] Figure 1-23. RAM Sleep Mode Control Register4 [0x1C2C] Figure 1-24. RAM Sleep Mode Control Register5 [0x1C2D] 1.5.5 Power Configurations Table 1-31. Power Configurations Page Page 1.6 Interrupts Interrupts Table 1-32. Interrupt Table (continued) 1.6.1 IFR and IER Registers Table 1-33. IFR0 and IER0 Bit Descriptions 1.6.2 InterruptTiming 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers 1.7 System Configuration and Control 1.7.1 Overview 1.7.2 DeviceIdentification Page Page Page 1.7.3 Device Configuration Table 1-44. EBSR Register Bit Descriptions Field Descriptions Page Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Figure 1-37. LDO Control Register (LDOCNTL) [7004h] Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions Table 1-47. LDO Controls Matrix Page Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued) Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued) Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions 1.7.4 DMA Controller Configuration Page Page 1.7.5 Peripheral Reset Page Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) 1.7.6 EMIF and USB Byte Access Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses Table 1-62. EMIF System Control Register (ESCR) Field Descriptions 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] IMPORTANT NOTICE