www.ti.com

System Configuration and Control

1.7.4.1DMA Synchronization Events

The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP supports 20 separate synchronization events and each channel can be tied to separate sync events independent of the other channels. Synchronization events are selected by programming the CHnEVT field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2) (where n is an integer, 0-3, representing each of the 4 DMAs). The synchronization events available to each DMA controller are shown in Table 1-52.

Table 1-52. Channel Synchronization Events for DMA Controllers

 

DMA0

DMA1

DMA2

DMA3 Synchronization

 

Synchronization

Synchronization

Synchronization

Event

CHmEVT Options

Event

Event

Event

 

 

 

 

 

 

0000b

Reserved

Reserved

Reserved

Reserved

 

 

 

 

 

0001b

I2S0 transmit event

I2S2 transmit event

I2C transmit event

I2S1 transit event

 

 

 

 

 

0010b

I2S0 receive event

I2S2 receive event

I2C receive event

I2S1 receive event

 

 

 

 

 

0011b

Reserved

Reserved

SAR A/D event

Reserved

 

 

 

 

 

0100b

Reserved

Reserved

I2S3 transmit event

Reserved

 

 

 

 

 

 

MMC/SD0 transmit

 

 

 

0101b

event

UART transmit event

I2S3 receive event

Reserved

 

 

 

 

 

0110b

MMC/SD0 receive

 

 

 

 

event

UART receive event

Reserved

Reserved

 

 

 

 

 

0111b

MMC/SD1 transmit

 

 

 

 

event

Reserved

Reserved

Reserved

 

 

 

 

 

1000b

MMC/SD1 receive

 

 

 

 

event

Reserved

Reserved

Reserved

 

 

 

 

 

1001b

Reserved

Reserved

Reserved

Reserved

 

 

 

 

 

1010v

Reserved

Reserved

Reserved

Reserved

 

 

 

 

 

1011b

Reserved

Reserved

Reserved

Reserved

 

 

 

 

 

1100b

Timer 0 event

Timer 0 event

Timer 0 event

Timer 0 event

 

 

 

 

 

1101b

Timer 1 event

Timer 1 event

Timer 1 event

Timer 1 event

 

 

 

 

 

1110b

Timer 2 event

Timer 2 event

Timer 2 event

Timer 2 event

 

 

 

 

 

1111b

Reserved

Reserved

Reserved

Reserved

 

 

 

 

 

1.7.4.2DMA Configuration Registers

The system-level DMA registers are listed in Table 1-53. The DMA interrupt flag and enable registers (DMAIFR and DMAIER) are used to control the aggregation and CPU interrupt generation for the four DMA controllers and their associated channels. In addition, there are two registers per DMA controller which control event synchronization in each channel; the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2).

Table 1-53. System Registers Related to the DMA Controllers

 

CPU Word

Acronym

Register Description

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

1C30h

DMAIFR

DMA Interrupt Flag Register

 

 

1C31h

DMAIER

DMA Interrupt Enable Register

 

 

1C1Ah

DMA0CESR1

DMA0 Channel Event Source Register 1

 

 

1C1Bh

DMA0CESR2

DMA0 Channel Event Source Register 2

 

 

1C1Ch

DMA1CESR1

DMA1 Channel Event Source Register 1

 

 

1C1Dh

DMA1CESR2

DMA1 Channel Event Source Register 2

 

 

1C36h

DMA2CESR1

DMA2 Channel Event Source Register 1

 

 

1C37h

DMA2CESR2

DMA2 Channel Event Source Register 2

 

 

1C38h

DMA3CESR1

DMA3 Channel Event Source Register 1

 

 

1C39h

DMA3CESR2

DMA3 Channel Event Source Register 2

 

 

 

 

 

 

 

 

 

SPRUFX5A –October 2010 –Revised November 2010

System Control 71

Submit Documentation Feedback

 

 

Copyright © 2010, Texas Instruments Incorporated

Page 71
Image 71
Texas Instruments TMS3320C5515 manual DMA Synchronization Events, Channel Synchronization Events for DMA Controllers

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.