Texas Instruments TMS3320C5515

Power Management

www.ti.com

Table 1-23. CPU Clock Domain Idle Requirements (continued)

ToIdle the Following Module/Port RequirementsBefore Going to Idle

XPORT CPUCPUI must also be set.

DPORT

1.5.3.1.3 Clock Configuration Process

The clock configuration indicates which portions of the CPU clock domain will be idle, and which will be

active. The basic steps to the clock configuration process are:

1. To idle MPORT, DMA controller, LCD DMA, and USB CDMA must not be accessing SARMA or

DARAM. If any DMA is in active, wait for completion of the DMA transfer.

2. Write the desired configuration to the idle configuration register (ICR). Make sure that you use a valid

idle configuration (see Section 1.5.3.1.2).

3. Apply the new idle configuration by executing the IDLE instruction. The content of ICR is copied to the

idle status register (ISTR). The bits of ISTR are then propagated through the CPU domain system to

enable or disable the specified clocks. If the CPU domain was idled, then program execution will stop

immediately after the idle instruction. If the CPU domain was not idled, then program execution will

continue past the idle instruction but the appropriate domains will be idle.

The IDLE instruction cannot be executed in parallel with another instruction.

The CPU, DPORT, XPORT, and IPORT domains are enabled automatically by any unmasked interrupts.

There is a logic in the DSP core that enables CPU, DPORT, XPORT, and IPORT (clears the bits 0, 5, 6,

and 8 of the ISTR register) asynchronously upon detecting an interrupt signal. Therefore, when an

unmasked interrupt signal reaches the DSP core, these domains are un-idled automatically. Once the

CPU is enabled, it takes 3 CPU cycles to detect the interrupt in the IFR. Note that HWA and MPORT have

to be manually enabled after being disabled.

1.5.3.2 Peripheral Domain Clock Gating

The peripheral clock gating allows software to disable clocks to the DSP peripherals, in order to reduce

the peripheral's active power consumption to zero. Aside from the analog logic, the DSP is designed in

static CMOS; thus, when a peripheral clock stops, the peripheral's state is preserved, and no active

current is consumed. When the clock is restarted the peripheral resumes operating from the stopping

point.

NOTE: Stopping clocks to a peripheral only affects active power consumption; it does not affect

leakage power consumption.

If a peripheral's clock is stopped while being accessed, the access may not occur completely, and could

potentially lock-up the device. To avoid this issue, some peripherals have a clock stop request and

acknowledge protocol that allows software to ask the peripheral when it is safe to stop the clocks. This is

described further in Section 1.5.3.2.2. For the peripherals that do not have the request/acknowledge

protocol, the user must ensure that all of the transactions to the peripheral are finished prior to stopping

the clocks.

The procedure to turn peripheral clocks on/off is described in Section 1.5.3.2.3.

Some peripherals provide additional power saving features by clock gating components within its

peripheral boundary. See the peripheral-specific user's guide for more details on these additional power

saving features.

38 SystemControl SPRUFX5A–October 2010 –Revised November 2010

SubmitDocumentation Feedback