Texas Instruments TMS3320C5515 Figure 1-2. DSP Memory Map

0001 0000h

64K Minus 192 Bytes

DARAM(D)

0009 0000h

SARAM 256K Bytes

External-CS2 Space(C)

0200 0000h

0300 0000h

0400 0000h

0500 0000h

050E 0000h

128K BytesAsynchronous (if MPNMC=1)

128K Bytes ROM (if MPNMC=0)

External-CS3 Space(C)

External-CS4 Space(C)

External-CS5 Space(C)

BLOCK SIZE

DMA/USB/LCD

BYTEADDRESS(A)

ROM

(if MPNMC=0)

External-CS5

f MPNMC=1)

(C)

Space

(i

1M Minus 128K BytesAsynchronous

1M BytesAsynchronous

2M BytesAsynchronous

4M BytesAsynchronous

MEMORYBLOCKS

0001 00C0h

MMR (Reserved)(B)

0100 0000h

External-CS0 Space(C)(E) 8M Minus 320K Bytes SDRAM/mSDRAM

050F FFFFh

000000h

010000h

800000h

C00000h

E00000h

F00000h

FE0000h

CPU BYTE

ADDRESS(A)

0000C0h

050000h

FFFFFFh

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System Memory

Figure 1-2. DSP Memory Map

A Addressshown represents the first byte address in each block.

B Thefirst 192 bytes are reserved for memory-mapped registers (MMRs).

C Outof the four DMA controllers, only DMA controller 3 has access to the external memory space.

D TheUSB controller does not have access to DARAM.

E TheCS0 space can be accessed by CS0 only or by CS0 and CS1.

1.2.1.1 On-ChipDual-Access RAM (DARAM)The DARAM is located in the CPU byte address range 00 00C0h - 00 FFFFh and is composed of eightblocks of 4K words each (see Table 1-2). Each DARAM block can perform two accesses per cycle (tworeads, two writes, or a read and a write). DARAM can be accessed by the internal program, data, andDMA buses.As shown in Table 1-2, the DMA controllers access DARAM at an address offset 0x0001_0000 from theCPU memory byte address space.Table 1-2. DARAM Blocks

MemoryBlock CPUByte Address Range DMA/USBController Byte Address Range

DARAM0 (1) 00 00C0h - 00 1FFFh 0001 00C0h - 0001 1FFFh

DARAM1 002000h - 00 3FFFh 00012000h - 0001 3FFFh

DARAM2 004000h - 00 5FFFh 00014000h - 0001 5FFFh

DARAM3 006000h - 00 7FFFh 00016000h - 0001 7FFFh

DARAM4 008000h - 00 9FFFh 00018000h - 0001 9FFFh

DARAM5 00A000h - 00 BFFFh 0001 A000h - 0001 BFFFh

(1) First192 bytes are reserved for memory-mapped registers (MMRs).

17

SPRUFX5A–October 2010 –Revised November 2010 SystemControl

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Contents

Main Page Contents Page Page Page Page Page Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Page Page Page Chapter 1 System Control 1.1 Introduction 1.1.1 BlockDiagram 1.1.2 CPU Core 1.1.3 FFT Hardware Accelerator 1.1.4 Power Management 1.1.5 Peripherals 1.2 System Memory 1.2.1 Program/DataMemory Map System Memory Figure 1-2. DSP Memory Map System Memory Table 1-2. DARAM Blocks (continued) Page 1.2.2 I/O Memory Map 1.3 Device Clocking 1.3.1 Overview Page Device Clocking www.ti.com Copyright 2010, Texas Instruments Incorporated Figure 1-3. DSP Clocking Diagram 22 SystemControl SPRUFX5AOctober 2010 Revised November 2010 SubmitDocumentation Feedback 1.3.2 Clock Domains 1.4 System Clock Generator 1.4.1 Overview ( ) 1.4.2 Functional Description Page 1.4.3 Configuration Page Page 1.4.4 Clock Generator Registers Page Page System Clock Generator Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions 1.5 Power Management 1.5.1 Overview 1.5.2 Power Domains Table 1-20. DSP Power Domains 1.5.3 Clock Management Page Figure 1-12. Idle Configuration Register (ICR) [0001h] Table 1-21. Idle Configuration Register (ICR) Field Descriptions Page Page Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued) Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions Page Page Page Page 1.5.4 Static Power Management Table 1-28. RTC Power Management Register (RTCPMGT) Field Descriptions Table 1-29. RTC Interrupt Flag Register (RTCINTFL) Field Descriptions Page Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A] Figure 1-22. RAM Sleep Mode Control Register3 [0x1C2B] Figure 1-23. RAM Sleep Mode Control Register4 [0x1C2C] Figure 1-24. RAM Sleep Mode Control Register5 [0x1C2D] 1.5.5 Power Configurations Table 1-31. Power Configurations Page Page 1.6 Interrupts Interrupts Table 1-32. Interrupt Table (continued) 1.6.1 IFR and IER Registers Table 1-33. IFR0 and IER0 Bit Descriptions 1.6.2 InterruptTiming 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers 1.7 System Configuration and Control 1.7.1 Overview 1.7.2 DeviceIdentification Page Page Page 1.7.3 Device Configuration Table 1-44. EBSR Register Bit Descriptions Field Descriptions Page Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Figure 1-37. LDO Control Register (LDOCNTL) [7004h] Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions Table 1-47. LDO Controls Matrix Page Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued) Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued) Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions 1.7.4 DMA Controller Configuration Page Page 1.7.5 Peripheral Reset Page Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) 1.7.6 EMIF and USB Byte Access Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses Table 1-62. EMIF System Control Register (ESCR) Field Descriptions 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] IMPORTANT NOTICE