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System Memory

Figure 1-2. DSP Memory Map

CPU BYTE

DMA/USB/LCD

 

 

ADDRESS(A)

BYTE ADDRESS(A)

 

 

 

 

 

 

 

MEMORY BLOCKS

 

 

 

 

 

 

 

 

000000h

0001

0000h

 

 

 

 

 

 

 

 

MMR (Reserved)(B)

 

 

 

 

 

 

0000C0h

0001 00C0h

 

 

 

 

 

 

 

 

DARAM(D)

 

 

 

 

 

 

 

 

010000h

0009

0000h

 

 

SARAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

050000h

0100 0000h

External-CS0 Space(C)(E)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

800000h

0200

0000h

External-CS2 Space(C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C00000h

0300

0000h

 

 

 

 

 

 

 

 

External-CS3 Space(C)

 

 

 

 

 

 

 

 

E00000h

0400

0000h

External-CS4 Space(C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F00000h

0500

0000h

External-CS5 Space(C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FE0000h

050E

0000h

 

 

 

 

 

 

 

 

ROM

 

External-CS5 Space(C)

 

 

 

 

 

(if MPNMC=0)

 

(if MPNMC=1)

FFFFFFh

050F FFFFh

 

 

 

BLOCK SIZE

64K Minus 192 Bytes

256K Bytes

8M Minus 320K Bytes SDRAM/mSDRAM

4M Bytes Asynchronous

2M Bytes Asynchronous

1M Bytes Asynchronous

1M Minus 128K Bytes Asynchronous

128K Bytes Asynchronous (if MPNMC=1)

128K Bytes ROM (if MPNMC=0)

AAddress shown represents the first byte address in each block.

BThe first 192 bytes are reserved for memory-mapped registers (MMRs).

COut of the four DMA controllers, only DMA controller 3 has access to the external memory space.

DThe USB controller does not have access to DARAM.

EThe CS0 space can be accessed by CS0 only or by CS0 and CS1.

1.2.1.1On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the CPU byte address range 00 00C0h - 00 FFFFh and is composed of eight blocks of 4K words each (see Table 1-2). Each DARAM block can perform two accesses per cycle (two reads, two writes, or a read and a write). DARAM can be accessed by the internal program, data, and DMA buses.

As shown in Table 1-2, the DMA controllers access DARAM at an address offset 0x0001_0000 from the CPU memory byte address space.

Table 1-2. DARAM Blocks

Memory Block

CPU Byte Address Range

DMA/USB Controller Byte Address Range

DARAM 0(1)

00 00C0h - 00 1FFFh

0001 00C0h - 0001 1FFFh

DARAM 1

00 2000h

- 00

3FFFh

0001 2000h

- 0001 3FFFh

DARAM 2

00 4000h

- 00

5FFFh

0001 4000h

- 0001

5FFFh

DARAM 3

00 6000h

- 00

7FFFh

0001 6000h

- 0001

7FFFh

DARAM 4

00 8000h

- 00

9FFFh

0001 8000h

- 0001

9FFFh

DARAM 5

00 A000h - 00

BFFFh

0001 A000h - 0001

BFFFh

 

 

 

 

 

 

 

(1)First 192 bytes are reserved for memory-mapped registers (MMRs).

SPRUFX5A –October 2010 –Revised November 2010

System Control 17

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Copyright © 2010, Texas Instruments Incorporated

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Texas Instruments TMS3320C5515 manual On-Chip Dual-Access RAM Daram, Daram Blocks, CPU Byte Address Range
Page 16 Page 18

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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