Texas Instruments TMS3320C5515 Functional Description, Multiplier and Dividers, Sysclk Frequency

System Clock Generator www.ti.com

Figure 1-4. Clock Generator

CLKSEL

CLKIN

RTC_CLKOUT RTC_XI

32.768	RTC
KHz	OSC
RTC_XO

1
	LS
0	CLKREF
RTC Clock
LS
RTC

	1					Output
				PLL		Divider
Reference		0	PLLIN		PLLOUT
Divider
CGCR2[RDBYPASS]

0
LS	1
1	SYSCLK
	0
CGCR4.
[OUTDIVEN]
	CCR2.
	[SYSCLKSEL]

1.4.2 Functional Description

The following sections describe the multiplier and dividers of the clock generator.

1.4.2.1Multiplier and Dividers

The clock generator has a one multiplier and a two programmable dividers: one before the PLL input and one on the PLL output. The PLL can be programmed to multiply the PLL input clock, PLLIN, using a x4 to x4099 multiplier value. The reference clock divider can be programmed to divide the clock generator input clock from a /4 to /4099 divider ratio and may be bypassed. The Reference Divider and RDBYPASS mux must be programmed such that the PLLIN frequency range is 32.786 KHz to 170 KHz. At the output of the PLL, the output divider can be used to divide the PLL output clock, PLLOUT, from a /1 to a /128 divider ratio and may also be bypassed. The PLL output, PLLOUT, frequency must be programmed within the range of at least 60 MHz and no more than the maximum operating frequency defined by the datasheet, Fsysclk_max parameter. See Table 1-10for allowed values of PLLIN, PLLOUT, and SYSCLK. Keep in mind that programming the output divider with an odd divisor value other than 1 will result in a non-50% duty cycle SYSCLK. This is not a problem for any of the on-chip logic, but the non-50% duty cycle will be visible on chip pins such as EM_SDCLK (in full-rate mode) and CLKOUT. See Table 1-10for allowed values of PLLIN, PLLOUT, and SYSCLK.

The multiplier and divider ratios are controlled through the PLL control registers. The M bits define the multiplier rate. The RDRATIO and ODRATIO bits define the divide ratio of the reference divider and programmable output divider, respectively. The RDBYPASS and OUTDIVEN bits are used to enable or bypass the dividers. Table 1-5lists the formulas for the output frequency based on the setting of these bits.

The clock generator must be placed in BYPASS MODE when any PLL dividers or multipliers are changed. Then, it must remain in BYPASS MODE for at least 4 mS before switching to PLL MODE.

Table 1-5. PLL Output Frequency Configuration

RDBYPASS	OUTDIVEN		SYSCLK Frequency
0	0	CLKREF ⋅			(M + 4 )
	RDRATIO + 4
0	1	CLKREF ⋅	(M + 4 )				⋅		1
	RDRATIO + 4				ODRATIO + 1
1	0		CLKREF ⋅ M + 4
								
1	1	CLKREF ⋅ M + 4⋅					1
						ODRATIO + 1

1.4.2.2Powering Down and Powering Up the System PLL

To save power, you can put the PLL in its power down mode. You can power down the PLL by setting the PLL_PWRDN = 1 in the clock generator control register CGCR1. However, before powering down the PLL, you must first place the clock generator in bypass mode.

24	System Control	SPRUFX5A –October 2010 –Revised November 2010
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