Texas Instruments TMS3320C5515 Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions

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The peripheral clock gating configuration register 2 (PCGCR2) is shown in Figure 1-15 and described in
Table 1-25.
Figure 1-15. Peripheral Clock Gating Configuration Register 2 (PCGCR2) [1C03h]
15 8
Reserved
R-0
76543210
Reserved ANAREGCG DMA3CG DMA2CG DMA1CG USBCG SARCG LCDCG
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND:R/W = Read/Write; R = Read only; -n= value after reset
Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions
Bit Field Value Description
15-7 Reserved 0 Reserved.
6 ANAREGCG Analogregisters clock gate control bit. This bit is used to enable and disable the clock to the
registersthat control the analog domain of the device, i.e. registers in the 7000h-70FFh I/O space
addressrange. NOTE When SARCG = 0, the clocks to the analog domain registers are enabled
regardlessof the ANAREGCG setting.
0 Clockis active.
1 Clockis disabled.
5 DMA3CG DMAcontroller 3 clock gate control bit. This bit is used to enable and disable the DMA controller 3
peripheralclock.
0 Peripheralclock is active.
1 Peripheralclock is disabled.
4 DMA2CG DMAcontroller 2 clock gate control bit. This bit is used to enable and disable the DMA controller 2
peripheralclock.
0 Peripheralclock is active.
1 Peripheralclock is disabled.
3 DMA1CG DMAcontroller 1 clock gate control bit. This bit is used to enable and disable the DMA controller 1
peripheralclock.
0 Peripheralclock is active.
1 Peripheralclock is disabled.
2 USBCG USBclock gate control bit. This bit is used to enable and disable the USB controller peripheral
clock.NOTE You must request permission before stopping the USB clock through the peripheral
clockstop request/acknowledge register (CLKSTOP). This register does not stop the USB PLL.
0 Peripheralclock is active.
1 Peripheralclock is disabled.
1 SARCG SARclock gate control bit. This bit is used to enable and disable the SAR peripheral clock. NOTE
WhenSARCG = 0, the clock to the analog domain registers is enabled regardless of the
ANAREGCGsetting.
0 Peripheralclock is active.
1 Peripheralclock is disabled.
0 LCDCG LCD controller clock gate control bit. This bit is used to enable and disable the LCD controller
peripheralclock.
0 Peripheralclock is active.
1 Peripheralclock is disabled.
41
SPRUFX5A–October 2010 –Revised November 2010 SystemControl
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