Texas Instruments TMS3320C5515 1.1.4 Power Management, 1.1.5 Peripherals

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Introduction

Note that for the FFT routines, output data is dependent on the return value (T0). If return = 0 output data

is in-place, meaning the result will overwrite the input buffer. If return =1, output data is placed in the

scratch buffer. The 32-bit input and output data consist of 16-bit real and 16-bit imaginary data. If only real

data is used, the imaginary part can be zeroed. The Scale flag determines if the butterfly output is divided

by 2 to prevent overflow at the expense of resolution. For further information on how to use these routines,

see FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (SPRABB6).

1.1.4 Power Management

Integrated into the C5515/14 DSP are the following power management features:

• One low dropout LDO for analog portions of the device, DSP PLL (VDDA_PLL), SAR, and power

management circuits (VDDA_ANA): ANA_LDO

• One LDO for DSP core (CVDD): DSP_LDO

• One LDO for USB core and PHY (USB_VDDA1P3): USB_LDO

• Idle controller with several clock domains:

– CPU domain

– Clock generator domain

– Peripheral domain

– USB domain

– Real-time clock (RTC) domain

• Independent voltage and power domains

• LDOI (LDOs and Bandgap Power Supply)

• Analog POR, SAR, and PLL (VDDA_ANA and VDDA_PLL)

• Real-time clock core (CVDDRTC)

• Digital core (CVDD)

• USB core (USB_ VDD1P3 and USB_VDDA1P3)

• USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL)

• EMIF I/O (DVDDEMIF)

• RTC I/O (DVDDRTC)

• Rest of the I/O (DVDDIO)

1.1.5 Peripherals

The DSP includes the following peripherals:

• Four direct memory access (DMA) controllers, each with four independent channels.

• One external memory interface (EMIF) with 21-bit address and 16-bit data. The EMIF has support for

mobile SDRAM and non-mobile SDRAM single-level cell (SCL) NAND with 1-bit ECC, and multi-level

cell (MLC) NAND with 4-bit ECC.

NOTE: The C5515 can support non-mobile SDRAM under certain circumstances. TheC5515

always uses mobile SDRAM initialization but it is able to support SDRAM memories that

ignore the BA0 and BA1 pins for the 'load mode register' command. During the mobile

SDRAM initialization, the device issues the 'load mode register' initialization command to two

different addresses that differ in only the BA0 and BA1 address bits. These registers are the

Extended Mode register and the Mode register. The Extended mode register exists only in

mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits BA0 and

BA1, the second loaded register value overwrites the first, leaving the desired value in the

Mode register and the non-mobile SDRAM will work with C5515.

• Two serial busses each configurable to support one Multimedia Card (MMC) / Secure Digital

(SD/SDIO) controller, one inter-IC sound bus (I2S) interface with GPIO, or a full GPIO interface.

• One parallel bus configurable to support a 16-bit LCD bridge or a combination of an 8-bit LCD bridge,

a serial peripheral interface (SPI), an I2S, a universal asynchronous receiver/transmitter (UART), and

GPIO.

• One inter-integrated circuit (I2C) multi-master and slave interface with 7-bit and 10-bit addressing

SPRUFX5A–October 2010 –Revised November 2010 SystemControl

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