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Introduction

Note that for the FFT routines, output data is dependent on the return value (T0). If return = 0 output data is in-place, meaning the result will overwrite the input buffer. If return =1, output data is placed in the scratch buffer. The 32-bit input and output data consist of 16-bit real and 16-bit imaginary data. If only real data is used, the imaginary part can be zeroed. The Scale flag determines if the butterfly output is divided by 2 to prevent overflow at the expense of resolution. For further information on how to use these routines, see FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (SPRABB6).

1.1.4 Power Management

Integrated into the C5515/14 DSP are the following power management features:

•One low dropout LDO for analog portions of the device, DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA): ANA_LDO

•One LDO for DSP core (CVDD): DSP_LDO

•One LDO for USB core and PHY (USB_VDDA1P3): USB_LDO

•Idle controller with several clock domains:

–CPU domain

–Clock generator domain

–Peripheral domain

–USB domain

–Real-time clock (RTC) domain

•Independent voltage and power domains

•LDOI (LDOs and Bandgap Power Supply)

•Analog POR, SAR, and PLL (VDDA_ANA and VDDA_PLL)

•Real-time clock core (CVDDRTC)

•Digital core (CVDD)

•USB core (USB_ VDD1P3 and USB_VDDA1P3)

•USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL)

•EMIF I/O (DVDDEMIF)

•RTC I/O (DVDDRTC)

•Rest of the I/O (DVDDIO)

1.1.5Peripherals

The DSP includes the following peripherals:

•Four direct memory access (DMA) controllers, each with four independent channels.

•One external memory interface (EMIF) with 21-bit address and 16-bit data. The EMIF has support for mobile SDRAM and non-mobile SDRAM single-level cell (SCL) NAND with 1-bit ECC, and multi-level cell (MLC) NAND with 4-bit ECC.

NOTE: The C5515 can support non-mobile SDRAM under certain circumstances. The C5515 always uses mobile SDRAM initialization but it is able to support SDRAM memories that ignore the BA0 and BA1 pins for the 'loadmode register'command. During the mobile SDRAM initialization, the device issues the 'loadmode register'initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register. The Extended mode register exists only in mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits BA0 and BA1, the second loaded register value overwrites the first, leaving the desired value in the Mode register and the non-mobile SDRAM will work with C5515.

•Two serial busses each configurable to support one Multimedia Card (MMC) / Secure Digital (SD/SDIO) controller, one inter-IC sound bus (I2S) interface with GPIO, or a full GPIO interface.

•One parallel bus configurable to support a 16-bit LCD bridge or a combination of an 8-bit LCD bridge, a serial peripheral interface (SPI), an I2S, a universal asynchronous receiver/transmitter (UART), and GPIO.

•One inter-integrated circuit (I2C) multi-master and slave interface with 7-bit and 10-bit addressing

SPRUFX5A –October 2010 –Revised November 2010

System Control

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Copyright © 2010, Texas Instruments Incorporated

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Texas Instruments TMS3320C5515 manual Power Management, Peripherals
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TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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