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System Configuration and Control

1.7.3 Device Configuration

The DSP includes registers for configuring pin multiplexing, the pin output slew rate, the internal pull-ups and pull-downs, DSP_LDO voltage selection and USB_LDO enable.

1.7.3.1External Bus Selection Register (EBSR)

The external bus selection register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3, UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. It also determines the mapping of the I2S or MMC/SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is located at port address 0x1C00. Once the bit fields of this register are changed, the routing of the signals takes place on the next CPU clock cycle.

Additionally, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15] can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE = 1, the EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin retains its EMIF functionality.

Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register (for more information on clock gating peripherals, see Section 1.5.3.2). After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register.

After the boot process is complete, the external bus selection register must be modified only once, during device configuration. Continuously switching the EBSR configuration is not supported.

The external bus selection register (EBSR) is shown in Figure 1-35and described in Table 1-44.

Figure 1-35. External Bus Selection Register (EBSR) [1C00h]

15

14

 

12

11

10

9

8

Reserved

 

PPMODE

 

SP1MODE

SP0MODE

 

 

 

 

 

 

R-0

 

R/W-000

 

R/W-00

R/W-00

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

Reserved

Reserved

A20_MODE

A19_MODE

A18_MODE

A17_MODE

A16_MODE

A15_MODE

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

SPRUFX5A –October 2010 –Revised November 2010

System Control

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Copyright © 2010, Texas Instruments Incorporated

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Texas Instruments TMS3320C5515 manual Device Configuration, External Bus Selection Register Ebsr
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TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

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In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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