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Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A]

15

14

13

12

11

10

9

8

SARAM7

SARAM7

SARAM6

SARAM6

SARAM5

SARAM5

SARAM4

SARAM4

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

 

 

 

 

 

 

 

 

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

SARAM3

SARAM3

SARAM2

SARAM2

SARAM1

SARAM1

SARAM0

SARAM0

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

 

 

 

 

 

 

 

 

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 1-22. RAM Sleep Mode Control Register3 [0x1C2B]

15

14

13

12

11

10

9

8

SARAM15

SARAM15

SARAM14

SARAM14

SARAM13

SARAM13

SARAM12

SARAM12

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

SARAM11

SARAM11

SARAM10

SARAM10

SARAM9

SARAM9

SARAM8

SARAM8

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

 

 

 

 

 

 

 

 

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 1-23. RAM Sleep Mode Control Register4 [0x1C2C]

15

14

13

12

11

10

9

8

SARAM23

SARAM23

SARAM22

SARAM22

SARAM21

SARAM21

SARAM20

SARAM20

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

SARAM19

SARAM19

SARAM18

SARAM18

SARAM17

SARAM17

SARAM16

SARAM16

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 1-24. RAM Sleep Mode Control Register5 [0x1C2D]

15

14

13

12

11

10

9

8

SARAM31

SARAM31

SARAM30

SARAM30

SARAM29

SARAM29

SARAM28

SARAM28

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

SARAM27

SARAM27

SARAM26

SARAM26

SARAM25

SARAM25

SARAM24

SARAM24

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

SLPZVDD

SLPZVSS

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

R/W+1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

SPRUFX5A –October 2010 –Revised November 2010

System Control

49

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Copyright © 2010, Texas Instruments Incorporated

Page 49
Image 49
Texas Instruments TMS3320C5515 manual RAM Sleep Mode Control Register2 0x1C2A

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.