Texas Instruments TMS3320C5515 Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions, Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions

System Clock Generator

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1.4.4.5 Clock Configuration Register 1 (CCR1) [1C1Eh]The clock configuration register 1 (CCR1) is shown in Figure 1-10 and described in Table 1-17.Figure 1-10. Clock Configuration Register 1 (CCR1) [1C1Eh]

15 1 0

Reserved SDCLK_EN

R-0 R/W-0

LEGEND:R = Read only; -n= value after reset

Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions

Bit Field Value Description

15-1 Reserved 0 Reserved.This bit must be kept as 0 during writes to this register.

0 SDCLK_EN SDRAMclock enable control. When ON, the EM_SDCLK pin will drive the clock signal at the

SYSCLKfrequency if in full_rate mode or at SYSCLK frequency divided by 2 if in half_rate mode.

WhenOFF, the EM_SDCLK pin will drive low. Transitions from ON to OFF and OFF to ON are not

guaranteedto be glitchless. Therefore, the EMIF should be reset after any change.

0 EM_SDCLKoff (default)

1 EM_SDCLKon. This bit must be set to 1 before using SDRAM or mSDRAM.

1.4.4.6 Clock Configuration Register 2 (CCR2) [1C1Fh]The clock configuration register 2 (CCR2) is shown in Figure 1-11 and described in Table 1-18.Figure 1-11. Clock Configuration Register 2 (CCR2) [1C1Fh]

15 6 5 4 3 2 1 0

Reserved SYSCLKSRC Reserved CLKSELSTAT Reserved SYSCLKSEL

R-0 R-0 R/W-0 R-0 R-0 R/W-0

LEGEND:R/W = Read/Write; R = Read only; -n= value after reset

Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions

Bit Field Value Description

15-6 Reserved 0 Reserved.

5-4 SYSCLKSRC System clock source status bits. These read-only bits reflect the source for the system clock. This

statusregister exists to indicate that switching from the PLL BYPASS_MODE to the PLL_MODE

wassuccessful or not. Logic exists on the chip to prevent switching to PLL_MODE if the PLL has its

PWRDNbit already asserted. However, this circuit does not protect against asserting the PWRDN

bitafter already in PLL_MODE. Therefore, software must ultimately make sure not to do something

thatwould cause the system clock to be lost.

0 Thesystem clock generator is in bypass mode; SYSCLK is driven by the RTC oscillator output.

1h The system clock generator is in PLL mode; the RTC oscillator output provides the input clock.

2h The system clock generator is in bypass mode; SYSCLK is driven by CLKIN.

3h The system clock generator is in PLL mode; the CLKIN pin provides the input clock.

3 Reserved 0 Reserved. This bit must be written to be 0.

2 CLKSELSTAT CLK_SELpin status bit. This reflects the state of the CLK_SEL pin.

0 CLK_SELpin is low (RTC input clock selected).

1 CLK_SELpin is high (CLKIN input clock selected).

1 Reserved 0 Reserved. This bit must be written to be 0.

0 SYSCLKSEL Systemclock source select bit. This bit is used to select between the two main clocking modes for

theDSP: bypass and PLL mode. In bypass mode, the DSP clock generator is bypassed and the

systemclock is set to either CLKIN or the RTC output (as determined by the CLKSEL pin). In PLL

mode,the system clock is set to the output of the DSP clock generator. Logic in the system clock

generatorprevents switching from bypass mode to PLL mode if the PLL is powered down.

0 Bypassmode is selected.

1 PLLmode is selected.

32 SystemControl SPRUFX5A–October 2010 –Revised November 2010

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