Manuals / Brands / Car Audio and Video / Car Stereo System / Texas Instruments / Car Audio and Video / Car Stereo System

Texas Instruments TMS3320C5515 1.7 System Configuration and Control 1.7.1 Overview, 1.7.2 DeviceIdentification

1 78

Download 78 pages, 418.73 Kb

www.ti.com

System Configuration and Control

1.7 System Configuration and Control1.7.1 Overview

The DSP includes system-level registers for controlling, configuring, and reading status of the device.

These registers are accessible by the CPU and support the following features:

• Device Identification

• Device Configuration

– Pinmultiplexing control

– Outputdrive strength configuration

– Internalpull-up and pull-down enable/disable

– On-chipLDO control

• DMA Controller Configuration

• Peripheral Reset

• EMIF and USB Byte Access

1.7.2 DeviceIdentification

The DSP includes a set of device ID registers that are intended for use in TI chip manufacturing, but can

be used by users as a 128-bit unique ID for each device. These registers are summarized in the following

table.

Table 1-35. Die ID Registers

CPUWord Acronym RegisterDescription Section

Address

1C40h DIEIDR0 DieID Register 0 Section1.7.2.1

1C41h DIEIDR1 DieID Register 1 Section1.7.2.2

1C42h DIEIDR2 DieID Register 2 Section1.7.2.3

1C43h DIEIDR3 DieID Register 3 Section1.7.2.4

1C44h DIEIDR4 DieID Register 4 Section1.7.2.5

1C45h DIEIDR5 DieID Register 5 Section1.7.2.6

1C46h DIEIDR6 DieID Register 6 Section1.7.2.7

1C47h DIEIDR7 DieID Register 7 Section1.7.2.8

57

SPRUFX5A–October 2010 –Revised November 2010 SystemControl

SubmitDocumentation Feedback

Copyright© 2010, Texas Instruments Incorporated

Contents

Main Page Contents Page Page Page Page Page Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Page Page Page Chapter 1 System Control 1.1 Introduction 1.1.1 BlockDiagram 1.1.2 CPU Core 1.1.3 FFT Hardware Accelerator 1.1.4 Power Management 1.1.5 Peripherals 1.2 System Memory 1.2.1 Program/DataMemory Map System Memory Figure 1-2. DSP Memory Map System Memory Table 1-2. DARAM Blocks (continued) Page 1.2.2 I/O Memory Map 1.3 Device Clocking 1.3.1 Overview Page Device Clocking www.ti.com Copyright 2010, Texas Instruments Incorporated Figure 1-3. DSP Clocking Diagram 22 SystemControl SPRUFX5AOctober 2010 Revised November 2010 SubmitDocumentation Feedback 1.3.2 Clock Domains 1.4 System Clock Generator 1.4.1 Overview ( ) 1.4.2 Functional Description Page 1.4.3 Configuration Page Page 1.4.4 Clock Generator Registers Page Page System Clock Generator Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions 1.5 Power Management 1.5.1 Overview 1.5.2 Power Domains Table 1-20. DSP Power Domains 1.5.3 Clock Management Page Figure 1-12. Idle Configuration Register (ICR) [0001h] Table 1-21. Idle Configuration Register (ICR) Field Descriptions Page Page Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued) Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions Page Page Page Page 1.5.4 Static Power Management Table 1-28. RTC Power Management Register (RTCPMGT) Field Descriptions Table 1-29. RTC Interrupt Flag Register (RTCINTFL) Field Descriptions Page Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A] Figure 1-22. RAM Sleep Mode Control Register3 [0x1C2B] Figure 1-23. RAM Sleep Mode Control Register4 [0x1C2C] Figure 1-24. RAM Sleep Mode Control Register5 [0x1C2D] 1.5.5 Power Configurations Table 1-31. Power Configurations Page Page 1.6 Interrupts Interrupts Table 1-32. Interrupt Table (continued) 1.6.1 IFR and IER Registers Table 1-33. IFR0 and IER0 Bit Descriptions 1.6.2 InterruptTiming 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers 1.7 System Configuration and Control 1.7.1 Overview 1.7.2 DeviceIdentification Page Page Page 1.7.3 Device Configuration Table 1-44. EBSR Register Bit Descriptions Field Descriptions Page Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Figure 1-37. LDO Control Register (LDOCNTL) [7004h] Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions Table 1-47. LDO Controls Matrix Page Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued) Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued) Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions 1.7.4 DMA Controller Configuration Page Page 1.7.5 Peripheral Reset Page Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) 1.7.6 EMIF and USB Byte Access Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses Table 1-62. EMIF System Control Register (ESCR) Field Descriptions 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] IMPORTANT NOTICE