System Configuration and Control
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Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses
BYTEMODESetting CPUAccess to EMIF Register CPUAccess To External Memory
BYTEMODE= 00b (16-bit Entireregister contents are accessed ASIZE= 01b (16-bit data bus): EMIF generates a
wordaccess) single16-bit access to external memory for every
CPUword access.
ASIZE= 00b (8-bit data bus): EMIF generates two
8-bitaccesses to external memory for every CPU
wordaccess.
BYTEMODE= 01b (8-bit Onlythe upper byte of the register is ASIZE = 01b (16-bit data bus): EMIF generates a
accesswith high byte selected) accessed. 16-bitaccess to external memory for every CPU word
access;only the high byte of the EMIF data bus is
used.
ASIZE= 00b (8-bit data bus): EMIF generates a
single8-bit access to external memory for every CPU
wordaccess.
BYTEMODE= 10b (8-bit Onlythe lower byte of the register is ASIZE = 01b (16-bit data bus): EMIF generates a
accesswith low byte selected) accessed. 16-bitaccess to external memory for every CPU word
access;only the low byte of the EMIF data bus is
used.
ASIZE= 00b (8-bit data bus): EMIF generates a
single8-bit access to external memory for every CPU
wordaccess.
The USB system control register (USBSCR) is described in Section 1.5.3.4.2.Table 1-61. Effect of USBSCR BYTEMODE Bits on USB Access
BYTEMODESetting CPUAccess to USB Register
BYTEMODE= 00b (16-bit word access) Entireregister contents are accessed
BYTEMODE= 01b (8-bit access with high byte selected) Onlythe upper byte of the register is accessed
BYTEMODE= 10b (8-bit access with low byte selected) Onlythe lower byte of the register is accessed
1.7.6.1 EMIF System Control Register (ESCR) [1C33h]The EMIF system control register (ESCR) is shown in Figure 1-48 and described in Table 1-62.Figure 1-48. EMIF System Control Register (ESCR) [1C33h]
15 2 1 0
Reserved BYTEMODE
R-0 R/W-0
LEGEND:R/W = Read/Write; R = Read only; -n= value after reset
Table 1-62. EMIF System Control Register (ESCR) Field Descriptions
Bit Field Value Description
15-2 Reserved 0 Reserved.
1-0 BYTEMODE EMIFbyte mode select bits. These bits control CPU data and program accesses to external
memoryas well as CPU accesses the EMIF registers.
0 Wordaccesses by the CPU are allowed.
1h Byte accesses by the CPU are allowed (high byte is selected).
2h Byte accesses by the CPU are allowed (low byte is selected).
3h Reserved.
76 SystemControl SPRUFX5A–October 2010– Revised November 2010
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