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Texas Instruments TMS3320C5515 Figure 1-12. Idle Configuration Register (ICR) [0001h], Table 1-21. Idle Configuration Register (ICR) Field Descriptions

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1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h]Table 1-21 describes the read/write bits of ICR, and Table 1-22 describes the read-only bits of ISTR.

NOTE: To prevent an emulation lock up, idle requests to these domains may be overridden or

ignored when an emulator is connected to the JTAG port of the DSP.

Figure 1-12. Idle Configuration Register (ICR) [0001h]

15 10 9 8

Reserved HWAI IPORTI

R/W-0 R/W-0 R/W-0

7654 10

MPORTI XPORTI DPORTI IDLECFG CPUI

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND:R/W = Read/Write; -n= value after reset

Table 1-21. Idle Configuration Register (ICR) Field Descriptions

Bit Field Value Description

15-10 Reserved 0 Reserved.

9 HWAI FFThardware accelerator idle control bit.

0 Hardwareaccelerator remains active after execution of an IDLE instruction.

1 Hardwareaccelerator is disabled after execution of an IDLE instruction.

8 IPORTI Instructionport idle control bit. The IPORT is used for all external memory instruction accesses.

0 IPORTremains active after execution of an IDLE instruction.

1 IPORTis disabled after execution of an IDLE instruction.

7 MPORTI Memoryport idle control bit. The memory port is used for all DMA, LCD DMA, and USB CDMA

transactionsinto on-chip memory.

0 MPORTremains active after execution of an IDLE instruction.

1 MPORTis disabled after execution of an IDLE instruction.

6 XPORTI I/O port idle control bit. The XPORT is used for all CPU I/O memory transactions.

0 XPORTremains active after execution of an IDLE instruction.

1 XPORTis disabled after execution of an IDLE instruction.

5 DPORTI Data port idle control bit. The data port is used for all CPU external memory data accesses.

0 DPORTremains active after execution of an IDLE instruction.

1 DPORTis disabled after execution of an IDLE instruction.

4-1 IDLECFG 0111b Idle configuration bits. You must always set bit 1, 2 and 3 to 1 and bit 4 to 0 before executing the

idleinstruction.

0 CPUI CPU idle control bit.

0 CPUremains active after execution of an IDLE instruction.

1 CPUis disabled after execution of an IDLE instruction.

36 SystemControl SPRUFX5A–October 2010 –Revised November 2010

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Contents

Main Page Contents Page Page Page Page Page Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Page Page Page Chapter 1 System Control 1.1 Introduction 1.1.1 BlockDiagram 1.1.2 CPU Core 1.1.3 FFT Hardware Accelerator 1.1.4 Power Management 1.1.5 Peripherals 1.2 System Memory 1.2.1 Program/DataMemory Map System Memory Figure 1-2. DSP Memory Map System Memory Table 1-2. DARAM Blocks (continued) Page 1.2.2 I/O Memory Map 1.3 Device Clocking 1.3.1 Overview Page Device Clocking www.ti.com Copyright 2010, Texas Instruments Incorporated Figure 1-3. DSP Clocking Diagram 22 SystemControl SPRUFX5AOctober 2010 Revised November 2010 SubmitDocumentation Feedback 1.3.2 Clock Domains 1.4 System Clock Generator 1.4.1 Overview ( ) 1.4.2 Functional Description Page 1.4.3 Configuration Page Page 1.4.4 Clock Generator Registers Page Page System Clock Generator Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions 1.5 Power Management 1.5.1 Overview 1.5.2 Power Domains Table 1-20. DSP Power Domains 1.5.3 Clock Management Page Figure 1-12. Idle Configuration Register (ICR) [0001h] Table 1-21. Idle Configuration Register (ICR) Field Descriptions Page Page Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued) Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions Page Page Page Page 1.5.4 Static Power Management Table 1-28. RTC Power Management Register (RTCPMGT) Field Descriptions Table 1-29. RTC Interrupt Flag Register (RTCINTFL) Field Descriptions Page Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A] Figure 1-22. RAM Sleep Mode Control Register3 [0x1C2B] Figure 1-23. RAM Sleep Mode Control Register4 [0x1C2C] Figure 1-24. RAM Sleep Mode Control Register5 [0x1C2D] 1.5.5 Power Configurations Table 1-31. Power Configurations Page Page 1.6 Interrupts Interrupts Table 1-32. Interrupt Table (continued) 1.6.1 IFR and IER Registers Table 1-33. IFR0 and IER0 Bit Descriptions 1.6.2 InterruptTiming 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers 1.7 System Configuration and Control 1.7.1 Overview 1.7.2 DeviceIdentification Page Page Page 1.7.3 Device Configuration Table 1-44. EBSR Register Bit Descriptions Field Descriptions Page Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Figure 1-37. LDO Control Register (LDOCNTL) [7004h] Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions Table 1-47. LDO Controls Matrix Page Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued) Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued) Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions 1.7.4 DMA Controller Configuration Page Page 1.7.5 Peripheral Reset Page Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) 1.7.6 EMIF and USB Byte Access Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses Table 1-62. EMIF System Control Register (ESCR) Field Descriptions 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] IMPORTANT NOTICE