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Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

5

A20PD

 

EMIF A[20] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

4

A19PD

 

EMIF A[19] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

3

A18PD

 

EMIF A[18] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

2

A17PD

 

EMIF A[17] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

1

A16PD

 

EMIF A[16] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

0

A15PD

 

EMIF A[15] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

The pull-down inhibit register 3 (PDINHIBR3) is shown in Figure 1-41and described in Table 1-51.

Figure 1-41. Pull-Down Inhibit Register 3 (PDINHIBR3) [1C19h]

15

14

13

12

11

10

9

8

PD15PD

PD14PD

PD13PD

PD12PD

PD11PD

PD10PD

PD9PD

 

PD8PD

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

 

R/W-1

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

PD7PD

PD6PD

PD5PD

PD4PD

PD3PD

PD2PD

 

Reserved

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

 

 

 

15

PD15PD

 

Parallel port pin 15 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

 

0

Pin pull-down is enabled.

 

 

 

 

1

Pin pull-down is disabled.

 

 

 

 

 

 

 

14

PD14PD

 

Parallel port pin 14 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

 

0

Pin pull-down is enabled.

 

 

 

 

1

Pin pull-down is disabled.

 

 

 

 

 

 

 

13

PD13PD

 

Parallel port pin 13 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

 

0

Pin pull-down is enabled.

 

 

 

 

1

Pin pull-down is disabled.

 

 

 

 

 

 

 

12

PD12PD

 

Parallel port pin 12 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

 

0

Pin pull-down is enabled.

 

 

 

 

1

Pin pull-down is disabled.

 

 

 

 

 

 

 

11

PD11PD

 

Parallel port pin 11 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

 

0

Pin pull-down is enabled.

 

 

 

 

1

Pin pull-down is disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPRUFX5A –October 2010 –Revised November 2010

System Control

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Copyright © 2010, Texas Instruments Incorporated

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Texas Instruments TMS3320C5515 manual A20PD, PD15PD
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TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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