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Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

2

S02PD

 

Serial port 0 pin 2 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

1

S01PD

 

Serial port 0 pin 1 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

0

S00PD

 

Serial port 0 pin 0 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.

 

 

0

Pin pull-down is enabled.

 

 

1

Pin pull-down is disabled.

 

 

 

 

The pull-down inhibit register 2 (PDINHIBR2) is shown in Figure 1-40and described in Table 1-50.

Figure 1-40. Pull-Down Inhibit Register 2 (PDINHIBR2) [1C18h]

15

 

14

13

12

11

10

9

8

Reserved

 

INT1PU

INT0PU

RESETPU

EMU01PU

TDIPU

TMSPU

TCKPU

 

 

 

 

 

 

 

 

 

R-0

R/W-1

R/W-1

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Reserved

 

A20PD

A19PD

A18PD

A17PD

A16PD

A15PD

R-0

 

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions

Bit

 

Field

Value

Description

 

 

 

 

 

15

 

Reserved

0

Reserved.

 

 

 

 

 

14

 

INT1PU

 

Interrupt 1 pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

13

 

INT0PU

 

Interrupt 0 pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

12

 

RESETPU

 

Reset pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

11

 

EMU01PU

 

EMU1 and EMU0 pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

10

 

TDIPU

 

TDI pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

9

 

TMSPU

 

TMS pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

8

 

TCKPU

 

TCK pin pull-up inhibit bit. Setting this bit to 1 disables the pin's internal pull-up.

 

 

 

0

Pin pull-up is enabled.

 

 

 

1

Pin pull-up is disabled.

 

 

 

 

 

7-6

 

Reserved

0

Reserved.

 

 

 

 

 

 

 

 

 

 

68

System Control

 

SPRUFX5A –October 2010 –Revised November 2010

 

 

 

 

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Texas Instruments TMS3320C5515 manual INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu Tckpu, A20PD A19PD A18PD A17PD A16PD A15PD

TMS3320C5515 specifications

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