Valid Idle Configurations | Texas Instruments TMS3320C5515 specification

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Figure 1-13. Idle Status Register (ISTR) [0002h]

15				10	9	8
		Reserved			HWAIS	IPORTIS

		R-0			R-0	R-0
7	6	5	4		1	0

MPORTIS	XPORTIS	DPORTIS	Reserved			CPUIS

R-0	R-0	R-0	R-0			R-0

LEGEND: R = Read only; -n= value after reset

Table 1-22. Idle Status Register (ISTR) Field Descriptions

Bit	Field	Value	Description

15-10	Reserved	0	Reserved.

9	HWAIS		FFT hardware accelerator idle status bit.
		0	Hardware accelerator is active.
		1	Hardware accelerator is disabled.

8	IPORTIS		Instruction port idle status bit. The IPORT is used for all external memory instruction accesses.
		0	IPORT is active.
		1	IPORT is disabled.

7	MPORTIS		Memory port idle status bit. The memory port is used for all DMA, LCD DMA, and USB CDMA
			transactions into on-chip memory.
		0	MPORT is active.
		1	MPORT is disabled.

6	XPORTIS		I/O port idle status bit. The XPORT is used for all CPU I/O memory transactions.
		0	XPORT is active.
		1	XPORT is disabled.

5	DPORTIS		Data port idle status bit. The data port is used for all CPU external memory data accesses.
		0	DPORT is active.
		1	DPORT is disabled.

4-1	Reserved	0	Reserved.

0	CPUIS		CPU idle status bit.
		0	CPU is active.
		1	CPU is disabled.

1.5.3.1.2 Valid Idle Configurations

Not all of the values that you can write to the idle configuration register (ICR) provide valid idle configurations. The valid configurations are limited by dependencies within the system. For example, the IDLECFG bits 1, 2 and 3 of ICR must always be set to 1, and bit 4 must always be cleared to 0. As another example, the XPORT cannot be idled unless the CPU is also idled. Before any part of the CPU domain is idled, you must observe the requirements outlined in Section 1.5.3.2.

A bus error will be generated (BERR = 1 in IFR1) if you execute the idle instruction under any of the following conditions and the idle command will not take effect:

1.If you fail to set IDLECFG = 0111 while setting any of these bits: DPORTI, XPORTI, IPORTI or

MPORTI.

2.If you set DPORTI, XPORTI, or IPORTI without also setting CPUI.

Table 1-23. CPU Clock Domain Idle Requirements

	To Idle the Following Module/Port	Requirements Before Going to Idle

	CPU	No requirements.
	FFT Hardware Accelerator	No requirements.
	MPORT	DMA controllers, LCD, and USB CDMA must not be accessing DARAM or SARAM.


SPRUFX5A –October 2010 –Revised November 2010			System Control 37
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TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.

Texas Instruments TMS3320C5515 manual Idle Status Register Istr Field Descriptions

Models: TMS3320C5515

Figure 1-13. Idle Status Register (ISTR) [0002h]

Table 1-22. Idle Status Register (ISTR) Field Descriptions

Bit

HWAIS

1.5.3.1.2 Valid Idle Configurations

Table 1-23. CPU Clock Domain Idle Requirements

MPORT

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TMS3320C5515 specifications