RTC Domain Clock Gating, Usbdatpol | Texas Instruments TMS3320C5515

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Table 1-27. USB System Control Register (USBSCR) Field Descriptions (continued)

Bit	Field	Value	Description

13	USBVBUSDET		USB VBUS detect enable. The USB VBUS pin has two comparators that monitor the
			voltage level on the pin. These comparators can be disabled for power savings when not
			needed.
		0	USB VBUS detect comparator is disabled.
		1	USB VBUS detect comparator is enabled.

12	USBPLLEN		USB PLL enable. This is normally only used for test purposes.
		0	Normal USB operation.
		1	Override USB suspend end behavior and force release of PLL from suspend state.

11-7	Reserved	0	Reserved. Always write 0 to these bits.

6	USBDATPOL		USB data polarity bit. Changing this bit can be useful since the data polarity is opposite
			on type-A and type-B connectors.
		0	Reverse polarity on DP and DM signals.
		1	Normal polarity (normal polarity matching pin names).

5-4	Reserved	0	Reserved.

3	USBOSCBIASDIS		USB internal oscillator bias resistor disable.
		0	Internal oscillator bias resistor enabled (normal operating mode).
		1	Internal oscillator bias resistor disabled. Disabling the internal resistor is primarily for
			production test purposes. But it can also be used when an external oscillator bias resistor
			is connected between the USB_MXI and USB_MXO pins (but this is not a recommended
			configuration).

2	USBOSCDIS		USB oscillator disable bit.
		0	USB internal oscillator enabled.
		1	USB internal oscillator disabled. Causes the USB_MXO pin to be tristated and the
			oscillator's clock into the core is forced low.

1-0	BYTEMODE		USB byte mode select bits.
		0	Word accesses by the CPU are allowed.
		1h	Byte accesses by the CPU are allowed (high byte is selected).
		2h	Byte accesses by the CPU are allowed (low byte is selected).
		3h	Reserved.

1.5.3.5RTC Domain Clock Gating

Dynamic RTC domain clock gating is not supported. Note that the RTC oscillator, and by extension the RTC domain, can be permanently disabled by not connecting a crystal and tying off the RTC oscillator pins. However, in this configuration, the RTC must still be powered and the RTC registers starting at I/O address 1900h will not be accessible. This includes the RTC Power Management Register (RTCPMGT) that provides powerdown control to the on-chip LDO and control of the WAKEUP and RTC_CLKOUT pins. See the device-specific data manual for more details on permanently disabling the RTC oscillator.

SPRUFX5A –October 2010 –Revised November 2010	System Control	45
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TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.

Texas Instruments TMS3320C5515 manual RTC Domain Clock Gating, Usbdatpol, Usboscbiasdis, Usboscdis

Models: TMS3320C5515

Table 1-27. USB System Control Register (USBSCR) Field Descriptions (continued)

Bit

USBDATPOL

USBOSCBIASDIS

USBOSCDIS

BYTEMODE

1.5.3.5RTC Domain Clock Gating

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TMS3320C5515 specifications