DSP Clocking Diagram | Texas Instruments TMS3320C5515 specification

Device Clocking

www.ti.com

Figure 1-3. DSP Clocking Diagram

CLKSEL

CLKIN

1

CLKREF

ST3_55[CLKOFF]

System Clock

LS

LS

1

CLKOUT

Generator

SYSCLK

0

(1)

(1)

(2)

0

ICR[HWAI]

PCGCR1

FFT Hardware

Accelerator

[SYSCLKDIS]

RTC Clock

ICR[MPORTI]

(1)

LS

CCR2

RTC_CLKOUT

[SYSCLKSEL]

MPORT Clock

RTC_XI

32.768

RTC

RTC

PCGCR1[DMA0CG]

ICR[XPORTI]

KHz

OSC

XPORT Clock

RTC_XO

DMA0

ICR[IPORTI]

PCGCR2[DMA1CG]

IPORT Clock

DMA1

ICR[DPORTI]

PCGCR2[DMA2CG]

DPORT Clock

USBPHYCLK

DMA2

ICR[CPUI]

PCGCR2[DMA3CG]

CPU Clock

DMA3

USB

PCGCR1[EMIFCG]

ECDR[EDIV]

PHY

60 MHz

÷2

0

USB

LS

EMIF

Digital

(1)

PCGCR2[USBCG]

1

USB_MXI

12 MHz

USB

USB

12 MHz

PCGCR1[SPICG]

OSC

PLL

PCGCR1[I2CCG]

UDB_MXO

LS

OFF

SPI

(1)

I2C

PCGCR1[I2S0CG]

PCGCR1[UARTCG]

USBSCR

UART

I2S0

[USBOSCDIS]

PCGCR1[I2S1CG]

PCGCR1[TMR2CG]
Timer2	I2S1
Timer2
PCGCR1[TMR1CG]	PCGCR1[I2S2CG]
PCGCR1[TMR1CG]
Timer1	I2S2
Timer1
PCGCR1[TMR0CG]	PCGCR1[I2S3CG]
PCGCR1[TMR0CG]
Timer0	I2S3
Timer0
	PCGCR2[SARCG]

SAR

PCGCR2[LCDCG]

LCD Controller

PCGCR1[MMCSD0CG]

MMC/SD0

PCGCR2[ANAREGCG]

PCGCR1[MMCSD1CG] MMC/SD1

Analog

Registers

(1)LS = Level Shifter

(2)The CLKOUT pin'soutput driver is enabled/disabled through the CLKOFF bit of the CPU ST3_55 register. At the beginning of the boot sequence, the on-chip Bootloader sets CLKOFF = 1 and CLKOUT pin is disabled (high-impedance). For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU Reference Guide (SWPU073).

22	System Control	SPRUFX5A –October 2010 –Revised November 2010
		Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Image 22

Texas Instruments TMS3320C5515 manual DSP Clocking Diagram

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.

Contents

Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block Diagram FFT Hardware Accelerator Using FFT Accelerator ROM routinesCPU Core Address Power Management Peripherals System Memory Program/Data Memory Map CPU Byte Address Range On-Chip Dual-Access RAM DaramDaram Blocks Daram Saram Blocks On-Chip Single-Access RAM SaramSaram External Memory On-Chip Single-Access Read-Only Memory SaromSarom Blocks Asynchronous Emif Interface 2 I/O Memory Map Overview Device Clocking DSP Clocking Diagram Clock Domains Functional Description PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Multiplier and Dividers SRC Clkout PinBit Field Value Description Clock Generator During Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator After Reset Entering and Exiting the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the PLL Mode Frequency Ranges for Internal Clocks Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name 10. PLL Clock Frequency Ranges Software Steps To Modify Multiplier and Divider Ratios Clock Generator RegistersLock Time 12. Clock Generator Registers Clock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 4 CGCR4 1C23h Clock Generator Control Register 3 CGCR3 1C22hInit Clock Configuration Register 2 CCR2 1C1Fh Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions 18. Clock Configuration Register 2 CCR2 Field Descriptions Power Domains 19. Power Management Features Power Domains Description 20. DSP Power DomainsClock Management CPU Domain Clock Gating Daram Hwai Iporti Mporti Xporti Dporti Idlecfg Cpui 21. Idle Configuration Register ICR Field DescriptionsHwai 22. Idle Status Register Istr Field Descriptions Valid Idle Configurations23. CPU Clock Domain Idle Requirements To Idle the Following Module/Port Clock Configuration ProcessPeripheral Domain Clock Gating Xport MMCSD0CG DMA0CG Uartcg Spicg I2S3CG Sysclkdis MMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg Anaregcg Usbclkstpack UrtclkstpackUrtclkstpreq Usbclkstpreq Bit Field Clock Generator Domain Clock GatingUSB Domain Clock Gating Emfclkstpack Usbpwdn Usbsessend Usbvbusdet Usbpllen USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions Usbpwdn Usboscbiasdis RTC Domain Clock GatingUsbdatpol Usboscdis Static Power Management RTC Power Management Register Rtcpmgt 1930h RTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field Descriptions Mode CV DD Voltage Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h 30. On-Chip Memory Standby Modes 21. RAM Sleep Mode Control Register2 0x1C2A DV DDRTC, Ldoi Power Configurations31. Power Configurations IDLE3 IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling 32. Interrupt Table HEX Bytes IFR and IER Registers 33. IFR0 and IER0 Bit Descriptions Rtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 Interrupt Timing34. IFR1 and IER1 Bit Descriptions Rtos Gpio Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hDMA Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID Registers Die ID Register 1 DIEIDR1 1C41h Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions 37. Die ID Register 1 DIEIDR1 Field Descriptions Die ID Register 4 DIEIDR4 1C44h Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions 40. Die ID Register 4 DIEIDR4 Field Descriptions Die ID Register 7 DIEIDR7 1C47h Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions 43. Die ID Register 7 DIEIDR7 Field Descriptions Device Configuration External Bus Selection Register Ebsr 44. Ebsr Register Bit Descriptions Field Descriptions A17MODE LDO Control Register 7004hLDO Control A16MODE 45. Rtcpmgt Register Bit Descriptions Field Descriptions Rtcpmgt Register Ldocntl Register 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Bgpd Bit Ldopd Bit Usbldoen Bit Clkoutsr Output Slew Rate Control Register Osrcr 1C16hEmifsr S15PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S05PD A20PD A19PD A18PD A17PD A16PD A15PD INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuINT1PU A20PD PD15PD DMA Controller Configuration 52. Channel Synchronization Events for DMA Controllers DMA Configuration RegistersDMA Synchronization Events 53. System Registers Related to the DMA Controllers 55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field Descriptions CH0EVT Peripheral ResetCH1EVT CH3EVT Count Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h PG4RST Emif and USB Byte Access PG3RST Bytemode Setting CPU Access to USB Register 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Emif System Control Register Escr 1C33h 63. Emif Clock Divider Register Ecdr Field Descriptions Emif Clock Divider Register Ecdr 1C26hEdiv DSP Products ApplicationsRfid