Chapter 3 Hardware
CoreModule 420 Reference Manual 37
Ethernet Interface (J2)The Ethernet solution is provided by the Intel 82551ER PCI controller chip and consists of both the
Media Access Controller (MAC) and the physical layer (PHY) combined into a single component
solution. The 82551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering
capabilities, which enables the 82551ER to perform high-speed data transfers over the internal PCI bus.
The 82551ER bus master capabilities enable the component to process high-level commands and
perform multiple operations, thereby off-loading communication tasks from the system CPU. The
Ethernet interface offers the following features:
•Full duplex or half-duplex support
•Full duplex support at 10Mbps or 100Mbps
•In full duplex mode the 82551ER adheres to the IEEE 802.3x Flow Control specification.
•In half-duplex mode, performance is enhanced by a proprietary collision reduction mechanism.
•IEEE 802.3 10/100BaseT compatible physical layer to wire transformer
•Two on board LEDs support the speed and the link and activity status
•10BaseT auto-polarity correction
•Data transmission with minimum interframe spacing (IFS).
•IEEE 802.3x auto-negotiation support for speed and duplex operation
•3kB transmit and 3kB receive FIFOs (helps prevent data underflow and overflow)
•IEEE 802.3x 100BaseTX flow control support
Table 3-16 describes the pin-outs of the Ethernet connector J2.
Table 3-16. Ethernet Interface Pin/Signal Descriptions (J2)
Pin # Signal Description
1TX+
2TX-
Analog Twisted Pair Ethernet Transmit Differential Pair – These pins transmit the
serial bit stream through the isolation transformer on the Unshielded Twisted Pair
Cable (UTP).
3RX+
6RX-
Analog Twisted Pair Ethernet Receive Differential Pair – These pins receive the
serial bit stream through the isolation transformer.
4 NU Not Used (RJ45 termination)
5 NU Not Used (RJ45 termination)
7 NU Not Used (RJ45 termination)
8 NU Not Used (RJ45 termination)
Note: NU = Not Used.