Chapter 3 | Hardware |
PC/104 Bus Interface (P1A,B,C,D)
The PC/104 Bus uses a
Table
Pin # | Signal | Description (P1 Row A) |
1 (A1) | IOCHCHK* | I/O Channel Check – This signal may be activated by ISA boards to |
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| request that a |
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| processor. It is driven active to indicate an uncorrectable error has been |
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| detected. |
2 (A2) | SD7 | System Data 7 – This signal (0 to 19) provides a system data bit. |
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3 (A3) | SD6 | System Data 6 – Refer to SD7, pin A2, for more information. |
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4 (A4) | SD5 | System Data 5 – Refer to SD7, pin A2, for more information. |
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5 (A5) | SD4 | System Data 4 – Refer to SD7, pin A2, for more information. |
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6 (A6) | SD3 | System Data 3 – Refer to SD7, pin A2, for more information. |
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7 (A7) | SD2 | System Data 2 – Refer to SD7, pin A2, for more information. |
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8 (A8) | SD1 | System Data 1 – Refer to SD7, pin A2, for more information. |
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9 (A9) | SD0 | System Data 0 – Refer to SD7, pin A2, for more information. |
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10 (A10) | IOCHRDY | I/O Channel Ready – This signal allows slower ISA boards to lengthen |
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| I/O or memory cycles by inserting wait states. This signal’s normal |
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| state is active high (ready). ISA boards drive the signal inactive low |
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| (not ready) to insert wait states. Devices using this signal to insert wait |
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| states should drive it low immediately after detecting a valid address |
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| decode and an active read, or write command. The signal is released |
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| high when the device is ready to complete the cycle. |
11 (A11) | AEn | Address Enable – This signal is reserved for the ISA Bus and is asserted |
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| during DMA cycles to prevent I/O slaves from misinterpreting DMA |
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| cycles as valid I/O cycles.. |
12 (A12) | SA19 | System Address 19 – This signal (0 to 19) provides a system address bit. |
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13 (A13) | SA18 | System Address 18 – Refer to SA19, pin A12, for more information. |
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14 (A14) | SA17 | System Address 17 – Refer to SA19, pin A12, for more information. |
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15 (A15) | SA16 | System Address 16 – Refer to SA19, pin A12, for more information. |
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16 (A16) | SA15 | System Address 15 – Refer to SA19, pin A12, for more information. |
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17 (A17) | SA14 | System Address 14 – Refer to SA19, pin A12, for more information. |
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18 (A18) | SA13 | System Address 13 – Refer to SA19, pin A12, for more information. |
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19 (A19) | SA12 | System Address 12– Refer to SA19, pin A12, for more information. |
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20 (A20) | SA11 | System Address 11 – Refer to SA19, pin A12, for more information. |
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21 (A21) | SA10 | System Address 10 – Refer to SA19, pin A12, for more information. |
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22 (A22) | SA9 | System Address 9 – Refer to SA19, pin A12, for more information. |
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23 (A23) | SA8 | System Address 8 – Refer to SA19, pin A12, for more information. |
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24 (A24) | SA7 | System Address 7 – Refer to SA19, pin A12, for more information. |
25 (A25) | SA6 | System Address 6 – Refer to SA19, pin A12, for more information. |
26 (A26) | SA5 | System Address 5 – Refer to SA19, pin A12, for more information. |
22 | Reference Manual | CoreModule 420 |
