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| Pin # | Signal | Description (P1 Row C) |
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| 6 (C5) | LA20 | Lactchable Address 20 – Refer to LA23, pin C2, for more information. |
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| 7 (C6) | LA19 | Lactchable Address 19 – Refer to LA23, pin C2, for more information. |
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| 8 (C7) | LA18 | Lactchable Address 18 – Refer to LA23, pin C2, for more information. |
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| 9 (C8) | LA17 | Lactchable Address 17 – Refer to LA23, pin C2, for more information. |
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| 10 | (C9) | MemR* | Memory Read – This signal instructs a selected memory device to drive |
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| data onto the data bus. It is active on all memory read cycles. |
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| 11 | (C10) | MemW* | Memory Write – This signal instructs a selected memory device to store |
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| data currently on the data bus. It is active on all memory write cycles. |
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| 12 | (C11) | SD8 | System Data 8 – Refer to SD7, pin A2, for more information. |
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| 13 | (C12) | SD9 | System Data 9 – Refer to SD7, pin A2, for more information. |
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| 14 | (C13) | SD10 | System Data 10 – Refer to SD7, pin A2, for more information. |
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| 15 | (C14) | SD11 | System Data 11 – Refer to SD7, pin A2, for more information. |
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| 16 | (C15) | SD12 | System Data 12 – Refer to SD7, pin A2, for more information. |
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| 17 | (C16) | SD13 | System Data 13 – Refer to SD7, pin A2, for more information. |
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| 18 | (C17) | SD14 | System Data 14 – Refer to SD7, pin A2, for more information. |
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| 19 | (C18) | SD15 | System Data 15 – Refer to SD7, pin A2, for more information. |
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| 20 | (C19) | Key (NC) | Key Pin (Not Connected) |
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Notes: The shaded area denotes power or ground. The signals marked with * indicate active low.
Table
Pin # | Signal | Description (P1 Row D) |
21 (D0) | GND | Ground |
22 (D1) | MCS16* | Memory Chip Select 16 – This is signal is driven low by a memory slave |
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| device to indicates it is cable of performing a |
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| transfer. This signal is driven from a decode of the LA23 to LA17 |
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| address lines. |
23 (D2) | IOCS16* | I/O Chip Select 16 – This signal is driven low by an I/O slave device to |
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| indicate it is capable of performing a |
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| signal is driven from a decode of the SA15 to SA0 address lines. |
24 (D3) | IRQ10 | Interrupt Request 10 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
25 (D4) | IRQ11 | Interrupt Request 11 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
26 (D5) | IRQ12 | Interrupt Request 12 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
27 (D6) | IRQ15 | Interrupt Request 15 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
28 (D7) | IRQ14 | Interrupt Request 14 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
29 (D8) | DAck0* | DMA Acknowledge 0 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control of |
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| the bus from the DMA controller. |
30 (D9) | DRQ0 | DMA Request 0 – Used by I/O resources to request DMA service. Must |
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| be held high until associated DACK0 line is active. |
CoreModule 420 | Reference Manual | 25 |
