Chapter 3 |
| Hardware | ||
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| Pin # | Signal | Description (P1 Row B) |
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| 49 (B17) | DAck1* | DMA Acknowledge 1 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control |
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| of the bus from the DMA controller. |
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| 50 (B18) | DRQ1 | DMA Request 1 – Used by I/O resources to request DMA service. |
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| Must be held high until associated DACK1 line is active. |
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| 51 (B19) | Refresh* | Memory Refresh – This signal is driven low to indicate a memory |
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| refresh cycle is in progress. Memory is refreshed every 15.6 usec. |
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| 52 (B20) | SysClk* | System Clock – This is a free running clock typically in the 8MHZ to |
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| 10MHz range, although its exact frequency is not guaranteed. |
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| 53 (B21) | IRQ7 | Interrupt Request 7 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
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| 54 (B22) | IRQ6 | Interrupt Request 6 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
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| 55 (B23) | IRQ5 | Interrupt Request 5 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
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| 56 (B24) | IRQ4 | Interrupt Request 4 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
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| 57 (B25) | IRQ3 | Interrupt Request 3 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
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| 58 (B26) | DAck2* | DMA Acknowledge 2 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control |
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| of the bus from the DMA controller. |
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| 59 (B27) | TC | Terminal Count – This signal is a pulse to indicate a terminal count has |
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| been reached on a DMA channel operation. |
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| 60 (B28) | BALE | Buffered Address Latch Enable – This signal is used to latch the LA23 |
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| to LA17 signals or decodes of these signals. Addresses are latched on |
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| the falling edge of BALE. It is forced high during DMA cycles. When |
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| used with AENx, it indicates a valid processor or DMA address. |
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| 61 (B29) | +5V | +5V power +/- 10% |
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| 62 (B30) | OSC | Oscillator – This clock signal operates at 14.3MHz. This signal is not |
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| synchronous with the system clock (SYSCLK). |
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| 63 (B31) | GND | Ground |
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| 64 (B32) | GND | Ground |
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Notes: The shaded area denotes power or ground. The signals marked with * indicate active low.
Table
Pin # | Signal | Description (P1 Row C) | |
1 (C0) | GND | Ground |
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2 (C1) | SBHE* | System Byte High Enable – This signal is driven low to indicate a transfer | |
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| of data on the high half of the data bus (D15 to D8). | |
3 (C2) | LA23 | Lactchable Address 23 | – This signal must be latched by the resource if the |
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| line is required for the entire data cycle. | |
4 (C3) | LA22 | Lactchable Address 22 | – Refer to LA23, pin C2, for more information. |
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5 (C4) | LA21 | Lactchable Address 21 | – Refer to LA23, pin C2, for more information. |
24 | Reference Manual | CoreModule 420 |