Chapter 3

Hardware

LVDS Interface

Table 3-26. LVDS Interface Pin/Signal Descriptions (J31)

Pin #

Signal

Description

Line

Channel

1

3.3V_Panel

+3.3V source

 

 

2

5V_Panel

+5V source

 

 

3

GND

Ground

NA

NA

4

GND

Ground

 

 

5

LVDS_Y0M

Data Negative Output

0

 

 

 

 

 

 

6

LVDS_Y0P

Data Positive Output

 

 

 

 

 

 

 

7

LVDS_Y1M

Data Negative Output

1

 

8

LVDS_Y1P

Data Positive Output

 

Channel 1

 

 

 

 

 

9

LVDS_Y2M

Data Negative Output

2

 

 

 

 

 

 

10

LVDS_Y2P

Data Positive Output

 

 

11

LVDS_CLKYM

Clock Negative Output

Clock

 

 

 

 

 

 

12

LVDS_CLKYP

Clock Positive Output

 

 

 

 

 

 

 

13

LVDS_Z0M

Data Negative Output

0

 

 

 

 

 

 

14

LVDS_Z0P

Data Positive Output

 

 

 

 

 

 

 

15

LVDS_Z1M

Data Negative Output

1

 

16

LVDS_Z1P

Data Positive Output

 

Channel 2

 

 

 

 

 

17

LVDS_Z2M

Data Negative Output

2

 

 

 

 

 

 

18

LVDS_Z2P

Data Positive Output

 

 

19

LVDS_CLKZM

Clock Negative Output

Clock

 

 

 

 

 

 

20

LVDS_CLKZP

Clock Positive Output

 

 

 

 

 

 

 

Notes: The shaded area denotes power or ground.

NOTE

Pins 5-12 constitute 1st channel interface of two channels, or a

 

single channel interface. Pins 13-20 constitute 2nd channel

 

interface of two channels.

 

 

58

Reference Manual

LittleBoard 550

Page 64
Image 64
Ampro Corporation Littleboard 550 manual Lvds Interface, Pin # Signal Description Line Channel