Chapter 3 | Hardware |
Pin # | Signal | Descriptions (J1 Row B) |
47 (B15) | DACK3* | DMA Acknowledge 3 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control of |
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| the bus from the DMA controller. |
48 (B16) | DRQ3 | DMA Request 3 – Used by I/O resources to request DMA service. Must |
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| be held high until associated DACK3 line is active. |
49 (B17) | DACK1* | DMA Acknowledge 1 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control of |
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| the bus from the DMA controller. |
50 (B18) | DRQ1 | DMA Request 1 – Used by I/O resources to request DMA service. Must |
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| be held high until associated DACK1 line is active. |
51 (B19) | REFRESH* | Memory Refresh – This signal is driven low to indicate a memory refresh |
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| cycle is in progress. Memory is refreshed every 15.6 usec. |
52 (B20) | SYSCLK | System Clock – This is a free running clock typically in the 8MHz to |
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| 10MHz range, although its exact frequency is not guaranteed. |
53 (B21) | IRQ7 | Interrupt Request 7 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
54 (B22) | IRQ6 | Interrupt Request 6 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
55 (B23) | IRQ5 | Interrupt Request 5 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
56 (B24) | IRQ4 | Interrupt Request 4 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
57 (B25) | IRQ3 | Interrupt Request 3 – Asserted by a device when it has pending interrupt |
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| request. Only one device may use the request line at a time. |
58 (B26) | DACK2* | DMA Acknowledge 2 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control of |
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| the bus from the DMA controller. |
59 (B27) | TC | Terminal Count – This signal is a pulse to indicate a terminal count has |
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| been reached on a DMA channel operation. |
60 (B28) | BALE | Buffered Address Latch Enable – This signal is used to latch the LA23 to |
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| LA17 signals or decodes of these signals. Addresses are latched on the |
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| falling edge of BALE. It is forced high during DMA cycles. When used |
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| with AENx, it indicates a valid processor or DMA address. |
61 (B29) | +5V | +5 volt power ±10% |
62 (B30) | OSC | Oscillator – This clock signal operates at 14.3MHz. This signal is not |
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| synchronous with the system clock (SYSCLK). |
63 (B31) | GND | Ground |
64 (B32) | GND | Ground |
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Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
32 | Reference Manual | LittleBoard 550 |
