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Analog Devices AD9912 specifications Typical Performance Characteristics, Video BW

Models: AD9912

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AD9912

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, AVDD3, and DVDD at nominal supply voltage; DAC RSET = 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference phase noise used for generating these plots.

	–50								10
									0			CARRIER:	98.6MHz
									0			SFDR:	–67dBc
												SFDR:	–67dBc
	–55								–10			FREQ. SPAN:	500MHz
									–10			RESOLUTION BW: 3kHz
												RESOLUTION BW: 3kHz
								(dBm)POWERSIGNAL	–20			VIDEO BW:	10kHz
(dBc)SFDR	–60								–20
(dBc)SFDR									–30


	–65								–40
	–65								–50
									–50
	–70								–60
	–70
									–70
	–75				+25°C				–80
	–75				–40°C
					–40°C
					+85°C				–90
	–80						-003		–100
	0	100	200	300	400	500	-003		0	100	200	300	400	500
	0	100	200	300	400	500	06763		0	100	200	300	400	500
			OUTPUT FREQUENCY (MHz)				06763				FREQUENCY (MHz)

Figure 3. Wideband SFDR vs. Output Frequency at −40°C, +25°C, and +85°C,	Figure 6. Wideband SFDR at 98.6 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)	SYSCLK = 1 GHz (SYSCLK PLL Bypassed)

06763-006

	–50
	–55
	–60
(dBc)	–65
SFDR	–65
SFDR
	–70
	–75				HIGH VDD
	–75				NORMAL VDD
					LOW VDD
	–80						-004
	0	100	200	300	400	500	-004
	0	100	200	300	400	500	06763
			OUTPUT FREQUENCY (MHz)				06763

Figure 4. Variation of Wideband SFDR vs. Frequency over DAC Power Supply

Voltage, SYSCLK = 1 GHz (SYSCLK PLL Bypassed)

	10
	0			CARRIER:	201.1MHz
	0			SFDR:	–61dBc
				SFDR:	–61dBc
	–10			FREQ. SPAN:	500MHz
	–10			RESOLUTION BW: 3kHz
				RESOLUTION BW: 3kHz
(dBm)	–20			VIDEO BW:	10kHz
	–20
	–30
POWER	–40
POWER	–50
SIGNAL	–60
SIGNAL	–70
	–70
	–80
	–90
	–100						-007
	0	100	200	300	400	500	-007
	0	100	200	300	400	500	06763
			FREQUENCY (MHz)				06763

Figure 7. Wideband SFDR at 201.1 MHz,

SYSCLK = 1 GHz (SYSCLK PLL Bypassed)

SIGNAL POWER (dBm)

10
0			CARRIER:	20.1MHz
0			SFDR:	–79dBc
			SFDR:	–79dBc
–10			FREQ. SPAN:	500MHz
–10			RESOLUTION BW: 3kHz
			RESOLUTION BW: 3kHz
–20			VIDEO BW:	10kHz
–20
–30
–40
–50
–60
–70
–80
–90
–100 0	100	200	300	400	500
		FREQUENCY (MHz)

		10
		0	CARRIER:	398.7MHz
		0	SFDR:	–59dBc
			SFDR:	–59dBc
		–10	FREQ. SPAN:	500MHz
		–10	RESOLUTION BW:	3kHz
			RESOLUTION BW:	3kHz
	(dBm)	–20	VIDEO BW:	10kHz
		–20
		–30
	POWER	–50
	SIGNAL	–40
	SIGNAL	–60
		–60
		–70
		–80
		–90
	-005	–100						-008
	-005	0	100	200	300	400	500	-008
	06763	0	100	200	300	400	500	06763
	06763			FREQUENCY (MHz)				06763

Figure 5. Wideband SFDR at 20.1 MHz,	Figure 8. Wideband SFDR at 398.7 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)	SYSCLK = 1 GHz (SYSCLK PLL Bypassed)

Rev. D Page 10 of 40

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Analog Devices AD9912 specifications Typical Performance Characteristics, Video BW

Contents

Applications FeaturesBasic Block Diagram General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseFunctional Description Sysclk InputsSysclk PLL Doubler Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40