Parameter Description | Analog Devices AD9912 guide

AD9912

CSB

SCLK

SDIO

tS

tDS

tCLK

tHIGH

tDH

BIT N

tLOW

BIT N + 1

tH

06763-048

Figure 56. Serial Control Port Timing—Write

Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams

Parameter	Description
tCLK	Period of SCLK
tDV	Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO)
tDS	Setup time between data and rising edge of SCLK
tDH	Hold time between data and rising edge of SCLK
tS	Setup time between CSB and SCLK
tH	Hold time between CSB and SCLK
tHI	Minimum period that SCLK should be in a logic high state
tLO	Minimum period that SCLK should be in a logic low state

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Analog Devices AD9912 specifications Parameter Description

Contents

Basic Block Diagram FeaturesApplications General Description Table of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input Parameter Min Typ Max Unit Test Conditions/Comments AC Specifications Avss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter Rating Input Pin No Output Pin Type Mnemonic Description PIN Configuration and Function Descriptions Ioupdate ResetGND Avss Outb Video BW Typical Performance Characteristics Absolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024  DAC Spectrum vs. Reconstruction Filter Response Fdbkin Inputs Sysclk PLL Doubler Sysclk InputsFunctional Description Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLL Harmonic Spur Reduction Output Clock Drivers and 2× Frequency Multiplier Spur Reduction Circuit Diagram Thermal Parameters Thermal Performance Default Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Supplies Power Supply Partitioning Operation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first order I15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB First Parameter Description PLL Register MAP HSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register Descriptions Register 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-Divider Register 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-Phase Register 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-Reserved Register 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur B Outline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71 Rev. D Page 40