Register 0x0200-HSTL Driver | Analog Devices AD9912 instruction

AD9912

DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201)

Register 0x0200—HSTL Driver

Table 32.

Bits	Bit Name	Description

4	OPOL	Output polarity. Setting this bit inverts the HSTL driver output polarity.
[3:2]	Reserved	Reserved.
[1:0]	HSTL output doubler	HSTL output doubler.
		01	= doubler disabled.
		10	= doubler enabled. When using doubler, Bit 5 in Register 0x0010 must also be set to 1.

Register 0x0201—CMOS Driver

Table 33.

Bits	Bit Name	Description

0	CMOS mux	This bit allows the user to select whether the CMOS driver output is divided by the S-divider.
		0	= S-divider input sent to CMOS driver.
		1	= S-divider output sent to CMOS driver. See Figure 39.

CALIBRATION (USER-ACCESSIBLE TRIM) (REGISTER 0x0400 TO REGISTER 0x0410)

Register 0x0400 to Register 0x040A—Reserved

Register 0x040B—DAC Full-Scale Current

Table 34.

Bits	Bit Name	Description
[7:0]	DAC full-scale current	DAC full-scale current, Bits[7:0]. See the Digital-to-Analog (DAC) Output section.

Register 0x040C—DAC Full-Scale Current (Continued)

Table 35.

Bits	Bit Name	Description

[9:8]	DAC full-scale current	DAC full-scale current, Bits[9:8]. See Register 0x040B.

Register 0x040D to Register 0x0410—Reserved

HARMONIC SPUR REDUCTION (REGISTER 0x0500 TO REGISTER 0x0509)

See the Harmonic Spur Reduction section.

Register 0x0500—Spur A

Table 36.

Bits	Bit Name	Description
7	HSR-A enable	Harmonic Spur Reduction A enable.
6	Amplitude gain × 2	Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[5:4]	Reserved	Reserved.
[3:0]	Spur A harmonic	Spur A Harmonic 1 to Spur A Harmonic 15. Allows user to choose which harmonic to eliminate.

Register 0x0501—Spur A (Continued)

Table 37.

Bits	Bit Name	Description

[7:0]	Spur A magnitude	Linear multiplier for Spur A magnitude.

Rev. D Page 36 of 40

Image 36

Analog Devices AD9912 Register 0x0200-HSTL Driver, Register 0x0201-CMOS Driver, Register 0x040C-DAC Full-Scale Current

Contents

Features Basic Block DiagramApplications General Description Table of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/Comments Avss − Absolute Maximum Ratings Thermal ResistanceESD Caution Parameter Rating PIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic Description Reset IoupdateGND Avss Outb Typical Performance Characteristics Video BW Absolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS DIGITAL-TO-ANALOG DAC Output Reconstruction FilterSolving this equation for FTW yields 1024  Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter Response Sysclk Inputs Functional DescriptionSysclk PLL Doubler Sysclk PLL Multiplier Sysclk PLL multiplier has a 1 GHz VCO at its coreDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLL Output Clock Drivers and 2× Frequency Multiplier Harmonic Spur Reduction Spur Reduction Circuit Diagram Thermal Performance Thermal Parameters POWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Power Supply Partitioning Supplies Serial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port MSB/LSB First Transfers Instruction Word 16 BitsRead Operations are changed to LSB first order Serial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10 Parameter Description Register MAP PLL HSR-A Register 0x0000-Serial Port Configuration Register 0x0010-Power-Down and EnablePower-up default is defined by the start-up pins Register Descriptions Register 0x0011-Reserved Register 0x0012-Reset Autoclearing Register 0x0013-Reset Not AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x01A7-FTW0 Frequency Tuning Word Register 0x01A8-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-Divider Register 0x01A9-FTW0 Frequency Tuning Word Register 0x01AA-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-Phase Register 0x0200-HSTL Driver Register 0x0201-CMOS DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-Reserved Register 0x0503-Spur a Register 0x0504-Spur aRegister 0x0505-Spur B Register 0x0506-Spur B Outline Dimensions Model Temperature Range Package Description Package Option Ordering GuideAD9912BCPZ1 AD9912BCPZ-REEL71 Rev. D Page 40