Register 0x01A9-FTW0 Frequency Tuning Word | Analog Devices AD9912

		AD9912

Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
Table 27.
Bits	Bit Name	Description
[31:24]	FTW0	These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
		of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant
		byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to
		the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
Table 28.
Bits	Bit Name	Description

[39:32]	FTW0	These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
		of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant
		byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to
		the FTW results in an instantaneous frequency jump but no phase discontinuity.

Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
Table 29.
Bits	Bit Name	Description
[47:40]	FTW0	These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
		of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant
		byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to
		the FTW results in an instantaneous frequency jump but no phase discontinuity.

Register 0x01AC—Phase
Table 30.
Bits	Bit Name	Description

[7:0]	DDS phase word	Allows the user to vary the phase of the DDS output. See the Direct Digital Synthesizer section.
		Register 0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary
		phase discontinuity may occur as the phase passes through 45° intervals.

Register 0x01AD—Phase (Continued)
Table 31.
Bits	Bit Name	Description
[13:8]	DDS phase word	Allows the user to vary the phase of the DDS output. See the Direct Digital Synthesizer section.
		Register 0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary
		phase discontinuity may occur as the phase passes through 45° intervals.

Rev. D Page 35 of 40

Image 35

Analog Devices AD9912 specifications Register 0x01A9-FTW0 Frequency Tuning Word, Register 0x01AA-FTW0 Frequency Tuning Word

Contents

General Description FeaturesBasic Block Diagram Applications Table of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input Parameter Min Typ Max Unit Test Conditions/Comments AC Specifications Avss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD Caution Input Pin No Output Pin Type Mnemonic Description PIN Configuration and Function Descriptions Outb ResetIoupdate GND Avss Video BW Typical Performance Characteristics Absolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yields DAC Spectrum vs. Reconstruction Filter Response Fdbkin Inputs Sysclk PLL Doubler Sysclk InputsFunctional Description External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential Inputs Harmonic Spur Reduction Output Clock Drivers and 2× Frequency Multiplier Spur Reduction Circuit Diagram Thermal Parameters Thermal Performance Default Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Supplies Power Supply Partitioning Operation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits Read I15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB First Parameter Description PLL Register MAP HSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pins Register 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-Divider Register 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-Divider Register 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning Word Register 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale Current Register 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur B Outline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1 Rev. D Page 40