AD9912
Parameter | Min | Typ | Max | Unit | Test Conditions/Comments |
SYSTEM CLOCK INPUT |
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| System clock inputs should always be ac- |
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| coupled (both |
SYSCLK PLL Bypassed |
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Input Capacitance |
| 1.5 |
| pF | |
Input Resistance | 2.4 | 2.6 | 2.9 | kΩ | Differential |
Internally Generated DC Bias Voltage2 | 0.93 | 1.17 | 1.38 | V |
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Differential Input Voltage Swing | 632 |
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| mV | Equivalent to 316 mV swing on each leg |
SYSCLK PLL Enabled |
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Input Capacitance |
| 3 |
| pF | |
Input Resistance | 2.4 | 2.6 | 2.9 | kΩ | Differential |
Internally Generated DC Bias Voltage2 | 0.93 | 1.17 | 1.38 | V |
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Differential Input Voltage Swing | 632 |
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| mV | Equivalent to 316 mV swing on each leg |
Crystal Resonator with SYSCLK PLL Enabled |
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Motional Resistance |
| 9 | 100 | Ω | 25 MHz, 3.2 mm × 2.5 mm AT cut |
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CLOCK OUTPUT DRIVERS |
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HSTL Output Driver |
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Differential Output Voltage Swing | 1080 | 1280 | 1480 | mV | Output driver static, see Figure 27 for |
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| output swing vs. frequency |
0.7 | 0.88 | 1.06 | V |
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CMOS Output Driver |
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| Output driver static, see Figure 28 and |
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| Figure 29 for output swing vs. frequency |
Output Voltage High (VOH) | 2.7 |
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| V | IOH = 1 mA, Pin 37 = 3.3 V |
Output Voltage Low (VOL) |
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| 0.4 | V | IOL = 1 mA, Pin 37 = 3.3 V |
Output Voltage High (VOH) | 1.4 |
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| V | IOH = 1 mA, Pin 37 = 1.8 V |
Output Voltage Low (VOL) |
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| 0.4 | V | IOL = 1 mA, Pin 37 = 1.8 V |
TOTAL POWER DISSIPATION |
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DDS Only |
| 637 | 765 | mW | |
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| passed and CMOS driver off; SYSCLK = 1 GHz; |
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| HSTL driver off; spur reduction off; fOUT = |
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| 200 MHz |
DDS with Spur Reduction On |
| 686 | 823 | mW | Same as “DDS Only” case, except both spur |
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| reduction channels on |
DDS with HSTL Driver Enabled |
| 657 | 788 | mW | Same as “DDS Only” case, except HSTL driver |
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| enabled |
DDS with CMOS Driver Enabled |
| 729 | 875 | mW | Same as “DDS Only” case, except CMOS |
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| driver and |
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| CMOS fOUT = 50 MHz |
DDS with HSTL and CMOS Drivers Enabled |
| 747 | 897 | mW | Same as “DDS Only” case, except both HSTL |
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| and CMOS drivers enabled; |
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| enabled and set to 4; CMOS fOUT = 50 MHz |
DDS with SYSCLK PLL Enabled |
| 648 | 777 | mW | Same as “DDS Only” case, except 25 MHz on |
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| SYCLK input and PLL multiplier = 40 |
| 13 | 16 | mW | Using either the | |
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| register or the PWRDOWN pin |
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1Pin 14 is in the AVDD3 group, but it is recommended that Pin 14 be tied to Pin 1.
2AVSS = 0 V.
Rev. D Page 4 of 40