Register 0x0503-Spur a | Analog Devices AD9912 specification

AD9912

Register 0x0503—Spur A (Continued)

Table 38.

Bits	Bit Name	Description
[7:0]	Spur A phase	Linear offset for Spur B phase.

Register 0x0504—Spur A (Continued)

Table 39.

Bits	Bit Name	Description
[8]	Spur A phase	Linear offset for Spur A phase.

Register 0x0505—Spur B

Table 40.

Bits	Bit Name	Description

7	HSR-B enable	Harmonic Spur Reduction B enable.
6	Amplitude gain × 2	Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[5:4]	Reserved	Reserved.
[3:0]	Spur B harmonic	Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate.

Register 0x0506—Spur B (Continued)

Table 41.

Bits	Bit Name	Description
[7:0]	Spur B magnitude	Linear multiplier for Spur B magnitude.

Register 0x0508—Spur B (Continued)

Table 42.

Bits	Bit Name	Description

[7:0]	Spur B phase	Linear offset for Spur B phase.

Register 0x0509—Spur B (Continued)

Table 43.

Bits	Bit Name	Description

8	Spur B phase	Linear offset for Spur B phase.

Rev. D Page 37 of 40

Image 37

Analog Devices AD9912 Register 0x0503-Spur a, Register 0x0504-Spur a, Register 0x0505-Spur B, Register 0x0506-Spur B

Contents

Basic Block Diagram FeaturesApplications General Description Table of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC Specifications Avss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter Rating Input Pin No Output Pin Type Mnemonic Description PIN Configuration and Function Descriptions Ioupdate ResetGND Avss Outb Video BW Typical Performance Characteristics Absolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024  DAC Spectrum vs. Reconstruction Filter Response Fdbkin Inputs Functional Description Sysclk InputsSysclk PLL Doubler Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLL Harmonic Spur Reduction Output Clock Drivers and 2× Frequency Multiplier Spur Reduction Circuit Diagram Thermal Parameters Thermal Performance POWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Supplies Power Supply Partitioning Serial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first order I15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB First Parameter Description PLL Register MAP HSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register Descriptions Register 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-Divider Register 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-Phase Register 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-Reserved Register 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur B Outline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71 Rev. D Page 40