Ordering Guide, AD9912BCPZ1, AD9912BCPZ-REEL71

			AD9912

ORDERING GUIDE
Model	Temperature Range	Package Description	Package Option
AD9912ABCPZ1, 2	−40°C to +85°C	64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]	CP-64-7
AD9912ABCPZ-REEL71, 2	−40°C to +85°C	64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]	CP-64-7
AD9912BCPZ1	−40°C to +85°C	64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]	CP-64-1
AD9912BCPZ-REEL71	−40°C to +85°C	64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]	CP-64-1
AD9912A/PCBZ1, 2		Evaluation Board
AD9912/PCBZ1		Evaluation Board

1Z = RoHS Compliant Part.

2Recommended for use in new designs; reference PCN 09-0156.

Rev. D Page 39 of 40

Page 39

Image 39

Analog Devices specifications Ordering Guide, Model Temperature Range Package Description Package Option, AD9912BCPZ1

Contents

General Description FeaturesBasic Block Diagram Applications Table of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC Specifications Avss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD Caution Input Pin No Output Pin Type Mnemonic Description PIN Configuration and Function Descriptions Outb ResetIoupdate GND Avss Video BW Typical Performance Characteristics Absolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yields DAC Spectrum vs. Reconstruction Filter Response Fdbkin Inputs Sysclk Inputs Functional DescriptionSysclk PLL Doubler External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential Inputs Harmonic Spur Reduction Output Clock Drivers and 2× Frequency Multiplier Spur Reduction Circuit Diagram Thermal Parameters Thermal Performance POWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Supplies Power Supply Partitioning Serial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits Read I15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB First Parameter Description PLL Register MAP HSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pins Register 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-Divider Register 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-Divider Register 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning Word Register 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale Current Register 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur B Outline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1 Rev. D Page 40

Analog Devices AD9912 Ordering Guide, Model Temperature Range Package Description Package Option

Models: AD9912

AD9912

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9912BCPZ1

AD9912BCPZ-REEL71