Canon QY8-1360-000 4-42, Part 4 Technical Reference, BJC-7100, DRAM controller, CPU interface

Part 4: Technical Reference BJC-7100

DRAM controller

The DRAM controller controls the 10-bit addressing, reading/writing, RAS/CAS, and refresh of the 8Mbit DRAMs (4Mbit ×2).

Chip select controller

The chip select controller shows that a valid address has been output for the set area. The chip select controller is connected to the CARTRIDGE button, RESUME button, POWER button, and printer controller.

Clock & power manager

The clock and power manager controls the transition to low power-consumption mode. The WAKE UP pin is connected to the reset IC, and inputs the request to wake up from low power-consumption mode.

2) Printer controller (IC2)

The printer controller includes the CPU interface, DRAM interface, Centronics interface controller, print head controller, data processing controller, and IO ports, etc.

CPU interface

The CPU interface controls the writing to and reading from the CPU in sync with a 20MHz external clock input.

DRAM interface

The DRAM interface controls the 10-bit address and 16-bit data bus, the reading and writing, RAS/CAS, and refresh of the 8Mbit DRAM through the DRAM bus, which is independent of the MPU bus.

Centronics interface controller

The Centronics interface controller uses handshaking using the BUSY and ACKNLG signals to receive the 8-bit parallel data sent in sync with the data strobe (STROBE) signal from the host PC. It also controls the other interface signals. The data received from the interfaces is stored in the DRAM receive buffer. The MPU analysis this data and, if deemed to be print data, it is processed by the DMA.

When the printer initialize (INIT) signal is input from the interface, the Centronics interface controller outputs a BUSY signal. When INT0 is output to the MPU, the printer is initialized after any print data in the print buffer has been printed.

Print head controller

To drive the print head, the print head controller outputs the block signal and heat enable signal at the same time as the print data read from the DRAM print buffer is sent as serial data to the print head.

The transfer of print data (IDATA OM, IDATA BK, IDATA PH, IDATA CL) to the print head is synchronized to the 5MHz clock HDCLK signal. The block signals (BE0, BE1, BE2, ODDE, and EVENE), the pulse signals (HEAT OM, HEAT BK, HEAT PH, and HEAT CL), and the head temperature signals (SHON OM, SHON BK, SHON, PH, and SHON CL) are output to drive the print head.

Data processing controller

The data processing controller processes the data in the print buffer by DMA.

The data processing controller performs palette expand processing of the print data for photo printing, 1200dpi smoothing, and conversion of the raster print data into column oriented print data

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