Cypress CY8C22113, CY8C22213 Register Map Bank 1 Table Configuration Space, June 3, + Feedback

CY8C22x13 Final Data Sheet2. Register Reference

Register Map Bank 1 Table: Configuration Space

Name	Addr (1,Hex)	Access	Name	Addr (1,Hex)	Access	Name	Addr (1,Hex)	Access	Name	Addr (1,Hex)	Access
PRT0DM0	00	RW		40			80			C0
PRT0DM1	01	RW		41			81			C1
PRT0IC0	02	RW		42			82			C2
PRT0IC1	03	RW		43			83			C3
PRT1DM0	04	RW		44		ASD11CR0	84	RW		C4
PRT1DM1	05	RW		45		ASD11CR1	85	RW		C5
PRT1IC0	06	RW		46		ASD11CR2	86	RW		C6
PRT1IC1	07	RW		47		ASD11CR3	87	RW		C7
	08			48			88			C8
	09			49			89			C9
	0A			4A			8A			CA
	0B			4B			8B			CB
	0C			4C			8C			CC
	0D			4D			8D			CD
	0E			4E			8E			CE
	0F			4F			8F			CF
	10			50			90		GDI_O_IN	D0	RW
	11			51			91		GDI_E_IN	D1	RW
	12			52			92		GDI_O_OU	D2	RW
	13			53			93		GDI_E_OU	D3	RW
	14			54		ASC21CR0	94	RW		D4
	15			55		ASC21CR1	95	RW		D5
	16			56		ASC21CR2	96	RW		D6
	17			57		ASC21CR3	97	RW		D7
	18			58			98			D8
	19			59			99			D9
	1A			5A			9A			DA
	1B			5B			9B			DB
	1C			5C			9C			DC
	1D			5D			9D		OSC_GO_EN	DD	RW
	1E			5E			9E		OSC_CR4	DE	RW
	1F			5F			9F		OSC_CR3	DF	RW
DBB00FN	20	RW	CLK_CR0	60	RW		A0		OSC_CR0	E0	RW
DBB00IN	21	RW	CLK_CR1	61	RW		A1		OSC_CR1	E1	RW
DBB00OU	22	RW	ABF_CR0	62	RW		A2		OSC_CR2	E2	RW
	23			63			A3		VLT_CR	E3	RW
DBB01FN	24	RW		64			A4		VLT_CMP	E4	R
DBB01IN	25	RW		65			A5			E5
DBB01OU	26	RW	AMD_CR1	66	RW		A6			E6
	27		ALT_CR0	67	RW		A7			E7
DCB02FN	28	RW		68			A8		IMO_TR	E8	W
DCB02IN	29	RW		69			A9		ILO_TR	E9	W
DCB02OU	2A	RW		6A			AA		BDG_TR	EA	RW
	2B			6B			AB		ECO_TR	EB	W
DCB03FN	2C	RW		6C			AC			EC
DCB03IN	2D	RW		6D			AD			ED
DCB03OU	2E	RW		6E			AE			EE
	2F			6F			AF			EF
	30			70		RDI0RI	B0	RW		F0
	31			71		RDI0SYN	B1	RW		F1
	32			72		RDI0IS	B2	RW		F2
	33			73		RDI0LT0	B3	RW		F3
	34		ACB01CR3	74	RW	RDIOLT1	B4	RW		F4
	35		ACB01CR0	75	RW	RDI0RO0	B5	RW		F5
	36		ACB01CR1	76	RW	RDI0RO1	B6	RW		F6
	37		ACB01CR2	77	RW		B7		CPU_F	F7	RL
	38			78			B8			F8
	39			79			B9			F9
	3A			7A			BA			FA
	3B			7B			BB			FB
	3C			7C			BC			FC
	3D			7D			BD			FD
	3E			7E			BE		CPU_SCR1	FE	#
	3F			7F			BF		CPU_SCR0	FF	#
Blank fields are Reserved and should not be accessed.						# Access is bit specific.

June 3, 2004 Document No. 38-12009 Rev. *E 12

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