Cypress CY8C22213 3. PLL Lock for Low Gain Setting Timing Diagram, CY8C22x13 Final Data Sheet

CY8C22x13 Final Data Sheet 3. Electrical Specifications

PLL

Enable

TPLLSLEWLOW 24 MHz

FPLL

PLL

1

Gain

Figure 3-3. PLL Lock for Low Gain Setting Timing Diagram

32K	32 kHz
Select

TOS

F32K2

Figure 3-4. External Crystal Oscillator Startup Timing Diagram

Jitter24M1

F24M

Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter32k

F32K2

Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram

June 3, 2004 Document No. 38-12009 Rev. *E 23

[+] Feedback