Cypress CY8C22213, CY8C22113 manual AC External Clock Specifications, AC Programming Specifications

CY8C22x13 Final Data Sheet 3. Electrical Specifications

3.4.6AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified.

Table 3-22. 5V AC External Clock Specifications

Symbol	Description	Min		Typ	Max	Units	Notes
FOSCEXT	Frequency	0	–		24.24	MHz
–	High Period	20.6	–		–	ns
–	Low Period	20.6	–		–	ns
–	Power Up IMO to Switch	150	–		–	∝s

Table 3-23. 3.3V AC External Clock Specifications

	Symbol	Description	Min		Typ	Max	Units	Notes
FOSCEXT		Frequency with CPU Clock divide by 1a	0	–		12.12	MHz
FOSCEXT		Frequency with CPU Clock divide by 2 or greaterb	0	–		24.24	MHz
–		High Period with CPU Clock divide by 1	41.7	–		–	ns
–		Low Period with CPU Clock divide by 1	41.7	–		–	ns
–		Power Up IMO to Switch	150	–		–	∝s

a.Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

b.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per- cent duty cycle requirement is met.

3.4.7AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified.

Table 3-24. AC Programming Specifications

Symbol	Description	Min	Typ	Max	Units	Notes
TRSCLK	Rise Time of SCLK	1	–	20	ns
TFSCLK	Fall Time of SCLK	1	–	20	ns
TSSCLK	Data Set up Time to Falling Edge of SCLK	40	–	–	ns
THSCLK	Data Hold Time from Falling Edge of SCLK	40	–	–	ns
FSCLK	Frequency of SCLK	0	–	8	MHz
TERASEB	Flash Erase Time (Block)	–	15	–	ms
TWRITE	Flash Block Write Time	–	30	–	ms
TDSCLK	Data Out Delay from Falling Edge of SCLK	–	–	45	ns

June 3, 2004 Document No. 38-12009 Rev. *E 29

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