Cypress CYD01S36V, CYD02S36V, CYD02S36VA, CYD04S36V, CYD09S36V, CYD18S36V Figure 8. Read Cycle

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Document Number: 38-06076 Rev. *G Page 16 of 28

Figure 8. Read Cycle[14, 33, 34, 35, 36]

Notes

33.OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.

34.ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.

35.The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.

36.Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.

Numbers are for reference only.

Switching Waveforms (continued)

tCH2 tCL2

tCYC2

tSC tHC

tSW tHW

tSA tHA

AnAn+1

CLK

R/W

ADDRESS

DATAOUT

An+2 An+3

tSC tHC

tOHZ

tOE

tOLZ

tDC

tCD2

tCKLZ

QnQn+1 Qn+2

1 Latency

BE0–BE3

tSB tHB

[+] Feedback

Contents

Main CYD01S36V CYD09S36V/CYD18S36V FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Features Functional Description Seamless Migration to Next-Generation Dual-Port Family CYD02S36V/36VA/CYD04S36V Document Number: 38-06076 Rev. *G Page 2 of 28 Logic Block Diagram Dual Ported Array CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 3 of 28 Pin Configurations A B C D CYD02S36V/36VA/CYD04S36V Pin Definitions Master Reset Mailbox Interrupts Address Counter and Mask Register Operations CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Counter Reset Operation Counter Load Operation Counter Increment Operation Counter Hold Operation Counter Interrupt Counter Readback Operation Retransmit Page CYD09S36V/CYD18S36V IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP Reset Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Page Page Maximum Ratings Operating Range Electrical Characteristics Capacitance Page Switching Characteristics JTAG Timing JTAG Switching Waveform Switching Waveforms Figure 8. Read Cycle Figure 9. Bank Select Read Figure 10. Read-to-Write-to-Read (OE = LOW)[36, 39, 40, 41, 42] CYD09S36V/CYD18S36V Figure 11. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42] Figure 12. Read with Address Counter Advance Figure 13. Write with Address Counter Advance Figure 14. Counter Reset Figure 15. Readback State of Address Counter or Mask Register A A n+3 A Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read[50, 51, 52] L_PORT R_PORT Figure 17. Counter Interrupt and Retransmit Figure 18. MailBox Interrupt Timing LLHHD H X L H X High-Z Outputs Disabled Ordering Information 512K 32K Package Diagrams BOTTOMVIEW 51-85108-*F REFERENCEJEDEC MO-192 TOPVIEW Package Diagrams TOPVIEW 51-85201-*A Figure 20. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B Document History Page Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

Cypress Figure 8. Read Cycle

Models: CYD01S36V CYD02S36V CYD02S36VA CYD04S36V CYD09S36V CYD18S36V