CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 18. MailBox Interrupt Timing[57, 58, 59, 60, 61]
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tCH2 | tCL2 |
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CLKL |
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L_PORT | 7FFFF | An | |
ADDRESS | |||
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| tSINT |
An+1 |
An+2 | An+3 |
INTR |
tCYC2 
tCH2 tCL2
CLKR
tSA tHA
tRINT
R_PORT | Am | Am+1 | 7FFFF | Am+3 | Am+4 |
ADDRESS |
Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 62, 63, 64]
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| CE0 | CE1 | R/W | DQ0 – DQ35 | ||||
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| X |
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| H | X | X | Deselected | |
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| X |
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| X | L | X | Deselected | |
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| X |
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| L | H | L | DIN | Write |
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| L |
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| L | H | H | DOUT | Read |
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| H |
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| L | H | X | Outputs Disabled | |||
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Notes
57.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
58.Address “7FFFF” is the mailbox location for R_Port of the
59.L_Port is configured for Write operation, and R_Port is configured for Read operation.
60.At least one byte enable (BE0 – BE3) is required to be active during interrupt operations.
61.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
62.OE is an asynchronous input signal.
63.When CE changes state, deselection and Read happen after one cycle of latency.
64.CE0 = OE = LOW; CE1 = R/W = HIGH.
Document Number: | Page 24 of 28 |
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