Cypress CYD01S36V, CYD02S36V, CYD02S36VA, CYD04S36V, CYD09S36V, CYD18S36V Figure 15. Readback State of Address Counter or Mask Register, A, A n+3 A

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Document Number: 38-06076 Rev. *G Page 21 of 28

Figure 15. Readback State of Address Counter or Mask Register[46, 47, 48, 49]

Notes

46.CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

47.Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.

48.Address in input mode. Host can drive address bus after tCKHZ.

49.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.

Switching Waveforms (continued)

CNTEN

CLK

tCH2 tCL2

tCYC2

ADDRESS

ADS

Qx-2 Qx-1 Qn

tSA tHA

tSAD tHAD

tSCN tHCN

LOAD

ADDRESS

EXTERNAL

tCD2

INTERNAL

ADDRESS An+1 An+2

tCKHZ

DATAOUT

n+3

Qn+1 Qn+2

An+3 An+4

tCKLZ

tCA2 or tCM2

READBACK

INTERNAL

COUNTER

ADDRESS

INCREMENT

EXTERNAL

A0–A16

[+] Feedback

Contents

Main CYD01S36V CYD09S36V/CYD18S36V FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Features Functional Description Seamless Migration to Next-Generation Dual-Port Family CYD02S36V/36VA/CYD04S36V Document Number: 38-06076 Rev. *G Page 2 of 28 Logic Block Diagram Dual Ported Array CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 3 of 28 Pin Configurations A B C D CYD02S36V/36VA/CYD04S36V Pin Definitions Master Reset Mailbox Interrupts Address Counter and Mask Register Operations CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Counter Reset Operation Counter Load Operation Counter Increment Operation Counter Hold Operation Counter Interrupt Counter Readback Operation Retransmit Page CYD09S36V/CYD18S36V IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP Reset Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Page Page Maximum Ratings Operating Range Electrical Characteristics Capacitance Page Switching Characteristics JTAG Timing JTAG Switching Waveform Switching Waveforms Figure 8. Read Cycle Figure 9. Bank Select Read Figure 10. Read-to-Write-to-Read (OE = LOW)[36, 39, 40, 41, 42] CYD09S36V/CYD18S36V Figure 11. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42] Figure 12. Read with Address Counter Advance Figure 13. Write with Address Counter Advance Figure 14. Counter Reset Figure 15. Readback State of Address Counter or Mask Register A A n+3 A Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read[50, 51, 52] L_PORT R_PORT Figure 17. Counter Interrupt and Retransmit Figure 18. MailBox Interrupt Timing LLHHD H X L H X High-Z Outputs Disabled Ordering Information 512K 32K Package Diagrams BOTTOMVIEW 51-85108-*F REFERENCEJEDEC MO-192 TOPVIEW Package Diagrams TOPVIEW 51-85201-*A Figure 20. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B Document History Page Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

Cypress Figure 15. Readback State of Address Counter or Mask Register, A, A n+3 A

Models: CYD01S36V CYD02S36V CYD02S36VA CYD04S36V CYD09S36V CYD18S36V