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Cypress CYD02S36VA, CYD09S36V, CYD18S36V, CYD01S36V, CYD04S36V manual Datain, Dataout, Read Write, Ads

Models: CYD18S36V CYD02S36VA CYD09S36V CYD04S36V CYD02S36V CYD01S36V

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							CYD01S36V
						CYD02S36V/36VA/CYD04S36V
						CYD09S36V/CYD18S36V
Switching Waveforms (continued)
		Figure 11. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42]
	tCH2	tCYC2	tCL2
	tCH2		tCL2
CLK
CE	tSC	tHC
	tSC	tHC
				tSW tHW
R/W	tSW	tHW
ADDRESS	An		An+1	An+2	An+3	An+4	An+5
ADDRESS	tSA	tHA		tSD tHD
	tSA	tHA		tSD tHD
DATAIN			tCD2	Dn+2	Dn+3
			tCD2				tCD2
DATAOUT				Qn			Qn+4
				tOHZ
OE			READ		WRITE		READ
			READ		WRITE		READ

Figure 12. Read with Address Counter Advance[41]

		tCYC2
	tCH2	tCL2
CLK
tSA		tHA
ADDRESS	An
tSAD		tHAD
ADS
				tSAD	tHAD
CNTEN
tSCN		tHCN		tSCN	tHCN
				tCD2
DATAOUT	Qx–1		Qx	Qn	Qn+1	Qn+2	Qn+3
	READ		tDC	READ WITH COUNTER	COUNTER HOLD	READ WITH COUNTER
	EXTERNAL			READ WITH COUNTER		READ WITH COUNTER
	ADDRESS

Document Number: 38-06076 Rev. *G

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Cypress CYD02S36VA, CYD09S36V, CYD18S36V Datain, Dataout, Read Write, Ads, Read with Counter Counter Hold External Address

Contents

Features Functional DescriptionSeamless Migration to Next-Generation Dual-Port Family Logic Block Diagram1 Dual Ported Array Pin Configurations DQ10R DQ12R DQ14R Pin Definitions Master Reset Mailbox InterruptsAddress Counter and Mask Register Operations19 CLK Mrst CNT/MSK Cntrst ADS Cnten Counter Reset OperationCounter Load Operation Operation Description Counter Hold Operation Mask Reset OperationCounter Increment Operation Counter Interrupt Counter, Mask, and Mirror Logic Block Diagram1 Performing a Pause/Restart Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Scan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit Size Instruction Identification Codes Description Reserved Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance Switching Characteristics Over the Operating Range Jtag Timing Port to Port DelaysMaster Reset Timing Parameter Description 167/133/100 Unit Min Jtag Switching Waveform Switching Waveforms CLK AddressData OUT ADDRESSB1 Address B2Data OUT Read No Operation Write Read Write DatainDataout ADS Address Internal ADS Cnten Read Reset Address Counter Write CLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address Internal Lport Data CLK LLport CLK R Counter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Lport 7FFFF Address CLK CE0 CE1Clkl INT R Ordering Information Package Diagrams Ball Fbga 17 x 17 mm BB256 Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Document History Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions REV ECN no

Switching Waveforms (continued)

Figure 11. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42]

CLK

ADDRESS

DATAIN

DATAOUT

READ

WRITE

Figure 12. Read with Address Counter Advance[41]

CLK

ADDRESS

ADS

DATAOUT

READ WITH COUNTER

COUNTER HOLD

EXTERNAL

ADDRESS