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Cypress CYD18S36V, CYD02S36VA, CYD09S36V, CYD01S36V manual Dual Ported Array, Logic Block Diagram1

Models: CYD18S36V CYD02S36VA CYD09S36V CYD04S36V CYD02S36V CYD01S36V

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Logic Block Diagram[1]

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

FTSELL

PORTSTD[1:0]L

DQ [35:0]L

BE [3:0]L

CE0L

CE1L

OEL

R/WL

CONFIG Block

Control

CONFIG Block

Control

FTSELR

PORTSTD[1:0]R

DQ [35:0]R

BE [3:0]R

CE0R

CE1R

OER

R/WR

Dual Ported Array

A[18:0]L CNT/MSKL

ADSL CNTENL CNTRSTL RETL CNTINTL CL

WRPL

	L	Arbitration Logic
BUSY
BUSY

Address &

Counter Logic

BUSYR

Address &

Counter Logic

A [18:0]R

CNT/MSKR

ADSR

CNTENR

CNTRSTR

RETR

CNTINTR

WRPR

INTL

Mailboxes

INTR

READYL

LowSPDL


		TRST
		TRST
			TMS
			TMS
JTAG			TDI
			TDI
			TDO
			TDO
			TCK
			TCK



RESET			MRST
			MRST
	READYR

LOGIC
LOGIC		LowSPDR
		LowSPDR

Note

1.18-Mbit device has 19 address bits, 9-Mbit device has 18 address bits, 4-Mbit device has 17 address bits, 2-Mbit device has 16 address bits, and 1-Mbit device has 15 address bits.

Document Number: 38-06076 Rev. *G

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Cypress CYD18S36V, CYD02S36VA, CYD09S36V, CYD01S36V, CYD04S36V manual Dual Ported Array, Logic Block Diagram1

Contents

Seamless Migration to Next-Generation Dual-Port Family FeaturesFunctional Description Logic Block Diagram1 Dual Ported Array Pin Configurations DQ10R DQ12R DQ14R Pin Definitions Address Counter and Mask Register Operations19 Master ResetMailbox Interrupts CLK Mrst CNT/MSK Cntrst ADS Cnten Counter Reset OperationCounter Load Operation Operation Description Counter Hold Operation Mask Reset OperationCounter Increment Operation Counter Interrupt Counter, Mask, and Mirror Logic Block Diagram1 Performing a Pause/Restart Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Scan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit Size Instruction Identification Codes Description Reserved Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance Switching Characteristics Over the Operating Range Jtag Timing Port to Port DelaysMaster Reset Timing Parameter Description 167/133/100 Unit Min Jtag Switching Waveform Switching Waveforms Data OUT CLKAddress Data OUT Read No Operation Write ADDRESSB1Address B2 Read Write DatainDataout ADS Address Internal ADS Cnten Read Reset Address Counter Write CLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address Internal Lport Data CLK LLport CLK R Counter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Lport 7FFFF Address CLK CE0 CE1Clkl INT R Ordering Information Package Diagrams Ball Fbga 17 x 17 mm BB256 Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Document History Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions REV ECN no

Logic Block Diagram[1]

Dual Ported Array

TRST

TMS

JTAG

TDI

TDO

TCK

RESET

MRST

READYR

LOGIC