Cypress CYD01S36V, CYD02S36V, CYD02S36VA, CYD04S36V, CYD09S36V, CYD18S36V Figure 14. Counter Reset

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Document Number: 38-06076 Rev. *G Page 20 of 28

Figure 14. Counter Reset [43, 44]

Notes

43.CE0 = BE0 – BE3 = LOW; CE1 = MRST = CNT/MSK = HIGH.

44.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.

45.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value

Switching Waveforms (continued)

CLK

ADDRESS

INTERNAL

CNTEN

ADS

DATAIN

ADDRESS

CNTRST

R/W

DATAOUT

AnAmAp

Ax01AnAmAp

Q1Qn

tCH2 tCL2

tCYC2

tSA tHA

tSW tHW

tSRST tHRST

tSD tHD

tCD2 tCD2

tCKLZ

[45]

RESET ADDRESS 0

COUNTER WRITE READ

ADDRESS 0 ADDRESS 1

READ READ

ADDRESS AnADDRESS Am

READ

[+] Feedback

Contents

Main CYD01S36V CYD09S36V/CYD18S36V FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Features Functional Description Seamless Migration to Next-Generation Dual-Port Family CYD02S36V/36VA/CYD04S36V Document Number: 38-06076 Rev. *G Page 2 of 28 Logic Block Diagram Dual Ported Array CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 3 of 28 Pin Configurations A B C D CYD02S36V/36VA/CYD04S36V Pin Definitions Master Reset Mailbox Interrupts Address Counter and Mask Register Operations CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Counter Reset Operation Counter Load Operation Counter Increment Operation Counter Hold Operation Counter Interrupt Counter Readback Operation Retransmit Page CYD09S36V/CYD18S36V IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP Reset Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Page Page Maximum Ratings Operating Range Electrical Characteristics Capacitance Page Switching Characteristics JTAG Timing JTAG Switching Waveform Switching Waveforms Figure 8. Read Cycle Figure 9. Bank Select Read Figure 10. Read-to-Write-to-Read (OE = LOW)[36, 39, 40, 41, 42] CYD09S36V/CYD18S36V Figure 11. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42] Figure 12. Read with Address Counter Advance Figure 13. Write with Address Counter Advance Figure 14. Counter Reset Figure 15. Readback State of Address Counter or Mask Register A A n+3 A Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read[50, 51, 52] L_PORT R_PORT Figure 17. Counter Interrupt and Retransmit Figure 18. MailBox Interrupt Timing LLHHD H X L H X High-Z Outputs Disabled Ordering Information 512K 32K Package Diagrams BOTTOMVIEW 51-85108-*F REFERENCEJEDEC MO-192 TOPVIEW Package Diagrams TOPVIEW 51-85201-*A Figure 20. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B Document History Page Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

Cypress Figure 14. Counter Reset

Models: CYD01S36V CYD02S36V CYD02S36VA CYD04S36V CYD09S36V CYD18S36V