CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G Page 17 of 28
Figure 9. Bank Select Read[37, 38]
Figure 10. Read-to-Write-to-Read (OE = LOW)[36, 39, 40, 41, 42]Notes
37.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
38. ADS = CNTEN= BE0 – BE3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
39.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
40.During “No Operation,” data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
41. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
42.CE0 = BE0 – BE3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0A1A2A3A4A5
Q4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tDC
tSD tHD
WRITE
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+2 An+3
Qn
tCKHZ
NO OPERATION
READ
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