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Cypress CYD04S36V, CYD02S36VA, CYD09S36V Instruction Identification Codes Description, Reserved

Models: CYD18S36V CYD02S36VA CYD09S36V CYD04S36V CYD02S36V CYD01S36V

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Table 6. Instruction Identification Codes

Instruction	Code	Description
EXTEST	0000	Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.

BYPASS	1111	Places the BYR between TDI and TDO.

IDCODE	1011	Loads the IDR with the vendor ID code and places the register between TDI and TDO.

HIGHZ	0111	Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.

CLAMP	0100	Controls boundary to 1/0. Places BYR between TDI and TDO.

SAMPLE/PRELOAD	1000	Captures the input/output ring contents. Places BSR between TDI and TDO.

NBSRST	1100	Resets the non-boundary scan logic. Places BYR between TDI and TDO.

RESERVED	All other codes	Other combinations are reserved. Do not use other than the above.

Document Number: 38-06076 Rev. *G

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Cypress CYD04S36V, CYD02S36VA, CYD09S36V, CYD18S36V, CYD01S36V manual Instruction Identification Codes Description, Reserved

Contents

Seamless Migration to Next-Generation Dual-Port Family FeaturesFunctional Description Dual Ported Array Logic Block Diagram1 DQ10R DQ12R DQ14R Pin Configurations Pin Definitions Address Counter and Mask Register Operations19 Master ResetMailbox Interrupts Operation Description Counter Reset OperationCounter Load Operation CLK Mrst CNT/MSK Cntrst ADS Cnten Counter Interrupt Mask Reset OperationCounter Increment Operation Counter Hold Operation Counter, Mask, and Mirror Logic Block Diagram1 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Performing a Pause/Restart Scan Register Sizes Register Name Bit Size Scan Chain for 18-Mbit Device Reserved Instruction Identification Codes Description Capacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range Switching Characteristics Over the Operating Range Parameter Description 167/133/100 Unit Min Port to Port DelaysMaster Reset Timing Jtag Timing Switching Waveforms Jtag Switching Waveform Data OUT CLKAddress Data OUT Read No Operation Write ADDRESSB1Address B2 ADS DatainDataout Read Write ADS Cnten Address Internal Counter Write Read Reset Address Load Readback Increment External Counter Address Internal CLK External Address A0-A16 Internal Address CLK R CLK LLport Lport Data CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Counter Interrupt and Retransmit17, 45, 53, 54, 55 INT R CLK CE0 CE1Clkl Lport 7FFFF Address Ordering Information Ball Fbga 17 x 17 mm BB256 Package Diagrams Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B REV ECN no Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History