Cypress CYD01S36V, CYD02S36VA, CYD09S36V, CYD18S36V, CYD04S36V Pin Configurations, DQ10R DQ12R DQ14R

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Pin Configurations

Figure 1. Pin Diagram - 256-Ball FBGA (Top View)

CYD01S36V/CYD02S36V/36VA/CYD04S36V/CYD09S36V/CYD18S36V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

DQ32L

DQ30L

DQ28L

DQ26L

DQ24L

DQ22L

DQ20L

DQ18L

DQ18R

DQ20R

DQ22R

DQ24R

DQ26R

DQ28R

DQ30R

DQ32R

B

DQ33L

DQ31L

DQ29L

DQ27L

DQ25L

DQ23L

DQ21L

DQ19L

DQ19R

DQ21R

DQ23R

DQ25R

DQ27R

DQ29R

DQ31R

DQ33R

NC

NC

REVL

NC

NC

NC

C

RETL

TRST

RETR

DQ34L

DQ35L

INTL

MRST

INTR

DQ35R

DQ34R

[2,3]

[2,5]

[2,5]

[2,4]

[2,5]

[2,5]

[2,5]

[2,5]

[2,3]

VREFL

VREFL

D

A0L

A1L

WRPL

FTSELL

LOWSP

VSS

VTTL

VTTL

VSS

LOWSP

FTSEL

WRPR

A1R

A0R

[2,3]

[2,4]

[2,3]

DL [2,4]

DR [2,4]

R [2,3]

[2,4]

[2,3]

CE1L

VDDIO

VDDIO

VDDIO

CE1R

E

A2L

A3L

CE0L

VDDIOL

VDDIOL

VDDIOL

VCORE

VCORE

CE0R

A3R

A2R

[11]

[10]

R

R

R

[10]

[11]

VDDIO

F

CNTINT

CNTINT

A4L

A5L

BE3L

VDDIOL

VSS

VSS

VSS

VSS

VSS

VSS

BE3R

A5R

A4R

L [12]

R

R [12]

REVL

VDDIO

G

A6L

A7L

BUSYL

VSS

VSS

VSS

VSS

VSS

VSS

BUSYR

A7R

A6R

BE2L

BE2R

[2,5]

[2,3]

R

[2,5]

H

A8L

A9L

CL

VTTL

VCORE

VSS

VSS

VSS

VSS

VSS

VSS

VCORE

VTTL

CR

A9R

A8R

J

A10L

A11L

VSS

PORTS

VCORE

VSS

VSS

VSS

VSS

VSS

VSS

VCORE

PORTS

VSS

A11R

A10R

TD1L[2,

TD1R[2,

4]

4]

K

VDDIO

A12L

A13L

OEL

BE1L

VDDIOL

VSS

VSS

VSS

VSS

VSS

VSS

BE1R

OER

A13R

A12R

R

A15L

VDDIO

A15R

L

ADSL

ADSR

A14L

BE0L

VDDIOL

VSS

VSS

VSS

VSS

VSS

VSS

BE0R

A14R

[6]

[11]

R

[11]

[6]

M

A16L

A17L

REVL

VDDIO

VDDIO

VDDIO

REVR

A17R

A16R

R/WL

VDDIOL

VDDIOL

VDDIOL

VCORE

VCORE

R/WR

[7]

[8]

[2,4]

R

R

R

[2,4]

[8]

[7]

PortST

PortST

CNT/M

N

A18L

A19L

CNT/M

VREFL

READY

REVL

VTTL

VTTL

REVR

READY

VREFR

A19R

A18R

D0L

D0R

SKR

[9]

[2,5]

SKL [10]

[2,4]

[2,4]

L [2,5]

[2,3]

[2,3]

R [2,5]

[2,4]

[2,4]

[10]

[2,5]

[9]

NC

NC

NC

NC

P

DQ16L

DQ17L

CNTEN

CNTRS

TCK

TMS

TDO

TDI

CNTRS

CNTEN

DQ17R

DQ16R

L [11]

TL [10]

[2,5]

[2,5]

[2,5]

[2,5]

TR [10]

R [11]

R

DQ15L

DQ13L

DQ11L

DQ9L

DQ7L

DQ5L

DQ3L

DQ1L

DQ1R

DQ3R

DQ5R

DQ7R

DQ9R

DQ11R

DQ13R

DQ15R

T

DQ14L

DQ12L

DQ10L

DQ8L

DQ6L

DQ4L

DQ2L

DQ0L

DQ0R

DQ2R

DQ4R

DQ6R

DQ8R

DQ10R

DQ12R

DQ14R

Notes

2.This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.

3.Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.

4.Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.

5.Leave this ball unconnected. For more information about this feature, contact Cypress Sales.

6.Leave this ball unconnected for 32K x 36configuration.

7.Leave this ball unconnected for a 64K x 36, 32K x 36 configurations.

8.Leave this ball unconnected for a 128K x 36, 64K x 36 and 32K x 36 configurations.

9.Leave this ball unconnected for a 256K x 36, 128K x 36, 64K x 36, and 32K x 36 configurations.

10.These balls are not applicable for CYD18S36V device. They need to be tied to VDDIO.

11.These balls are not applicable for CYD18S36V device. They need to be tied to VSS.

12.These balls are not applicable for CYD18S36V device. They need to be no connected.

Document Number: 38-06076 Rev. *G Page 3 of 28

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