Cypress CYD18S36V, CYD02S36VA, CYD09S36V, CYD01S36V Counter, Mask, and Mirror Logic Block Diagram1

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Figure 2. Counter, Mask, and Mirror Logic Block Diagram[1]

CNT/MSK

CNTEN

ADS

CNTRST

MRST

Bidirectional

Address

Lines

CLK

Decode

Logic

Mask

Register

Counter/

Address

Register

Address

Decode

RAM Array

From	17	Load/Increment
Address	Mirror		Counter
Lines		1		To Readback
		1		and Address
		0		Decode
From	17	0
Mask	Increment
Register	Logic	Wrap		17

From	17	17
Mask	17	Bit 0
From
	+1		Wrap
Counter		1		Wrap
			Detect
	+2	0
		1	17
				To
		0		Counter

Document Number: 38-06076 Rev. *G Page 8 of 28

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