HP 8-Channel 196 kSa/sec Digitizer plus DSP E1433A manual

HP E1433A User's Guide

The C-Language Host Interface Library

In the example above, Mainframe A contains the Slot 0 Controller for a multiple mainframe system. Mainframe A is connected to Mainframe B with a VXI-MXI interface, HP E1482B. To successfully manage this multiple mainframe environment, use the following guidelines.

￿Locate modules with logical addresses less than 128 in Mainframe A.

￿Locate modules with logical addresses greater than 127 in Mainframe B.

￿Locate the highest-numbered channels in Mainframe A.

￿Locate the last module in the module list specified in the call to e1432_assign_channels() in Mainframe A.

￿Locate the module that generates the group synchronization pulse in Mainframe A.

￿Locate the channels performing channel triggering in Mainframe A.

￿Locate the module with the shared sample clock in Mainframe A.

￿If you do not use a groupID with the call e1432_read_data(), empty the HP E1433As’ FIFOs in Mainframe B before Mainframe A. In other words, do not empty the FIFOs in Mainframe A unless you have emptied the FIFOs in Mainframe B. For more information about groupID see “Grouping of Channels/Modules.”

￿If more than two mainframes are needed, daisy-chain them together. Treat each mainframe after the first as a Mainframe B. See the example on the next page.

Phase Performance in Multiple Mainframe Measurements

Phase specifications are degraded by the delay that the inter-mainframe interface gives the sample clock. This delay is insignificant for many low-frequency applications because the phase error is proportional to frequency. A system with two VXI-MXI modules and a 1 meter cable, typically has a 76 nanosecond (ns) sample clock delay in Mainframe B. This corresponds to an additional 0.007 degree phase error at 256 Hz and an additional 0.55 degree phase error at 20 kHz.

A 4-meter cable adds approximately 18 ns of delay for a total of 94 ns clock delay in Mainframe B. This corresponds to an additional 0.0087 degree phase error at 256 Hz and an additional 0.68 degree phase error at 20 kHz.

The cable adds approximately 6 ns per meter of cable.

Each daisy-chained mainframe adds another increment of delay, but only for the additional cabling length.

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