HP Ski Simulator manual Register Names, IA-64 Registers

Ski IA-64 Simulator Reference Manual 1.0L

B Register Names

IA-64 registers are fully described in other documents. This appendix provides a list for convenience only. The register names are documented here as recognized by Ski and, in a few cases, don’t exactly match the names in other documents due to program limitations. For example, the floating point registers must be accessed in three pieces: the mantissa part, the sign part, and the (biased) exponent part. Similarly, the “Not a Thing” bits of the various registers are separate entities for Ski. Individual bits of complex registers such as the psr are documented here as well, corresponding to the names by which Ski recognizes them.

B.1	IA-64 Registers
al, ah, ax, eax		IA-32 Registers: al and ah are byte-wide, ax is al and ah taken together as two bytes, eax is four bytes
		wide with ax as the two least significant bytes.
ar0 - ar127		IA-64 Application Registers
b0 - b7		IA-64 Branch Registers
bl, bh, bx, ebx		IA-32 Registers: bl and bh are byte-wide, bx is bl and bh taken together as two bytes, ebx is four bytes
		wide with bx as the two least significant bytes.
bp, ebp		IA-32 Base Pointers: bp is two bytes wide, ebp is four bytes wide with bp as the two least significant
		bytes.
bsp		IA-64 Register Save Engine (RSE) Backing Store Pointer Register
bspst		IA-64 Register Save Engine (RSE) Backing Store Pointer Register for memory stores
ccv		IA-64 Compare and Exchange Value Register
cl, ch, cx, ecx		IA-32 Registers: cl and ch are byte-wide, cx is cl and ch taken together as two bytes, ecx is four bytes
		wide with cx as the two least significant bytes.
cmcv		IA-64 Corrected Machine Check Vector Register
cr0 - cr127		IA-64 Control Registers
cs		IA-32 Code Segment Register
csd		IA-32 Code Segment Register Descriptor
dbr0 - dbr15		IA-64 Data Breakpoint Registers
dcr		IA-64 Default Control Register
dl, dh, dx, edx		IA-32 Registers: dl and dh are byte-wide, dx is dl and dh taken together as two bytes, edx is four bytes
		wide with dx as the two least significant bytes.
di, edi		IA-32 Arithmetic Registers: di is two bytes wide, edi is four bytes wide with di as the two least
		significant bytes.
ds		IA-32 Data Segment Register
dsd		IA-32 Data Segment Register Descriptor
ec		IA-64 Epilog Count Register
eflags		IA-32 Flags Register
eflags.ac		IA-32 Alignment Check bit
eflags.af		IA-32 Auxiliary Carry Flag bit, also called the IA-32 Adjust Flag bit
eflags.be		IA-32 Below Equal Flag bit
eflags.cf		IA-32 Carry Flag bit

Copyright © 2000 Hewlett-Packard Co. Register Names B-1