Waveforms Maximum Mode | Intel 8086-2, 8086-1 specs

8086

WAVEFORMS (Continued)

MAXIMUM MODE (Continued)

231455 – 16

NOTES:

1.All signals switch between VOH and VOL unless otherwise specified.

2.RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

3.Cascade address is valid between first and second INTA cycle.

4.Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle.

5.Signals at 8284A or 8288 are shown for reference only.

6.The issuance of the 8288 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high 8288 CEN.

7.All timing measurements are made at 1.5V unless otherwise noted.

8.Status inactive in state just prior to T4.

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Intel 8086-2, 8086-1 manual Waveforms Maximum Mode

Contents

CPU Block Diagram Pin Configuration BHE LOW BHE/S Test ResetReady Intr RQ/GT1 LOWHigh RQ/GT0 DEN IntaALE DT/R Functional Description BUS Operation Minimum and Maximum Modes Minimum Mode 8086 Typical Configuration Read Data from Memory Read I/OWrite I/O Instruction Fetch Interrupt Operations Processor Reset and InitializationAlternate Data extra segment Addressing READ/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt System TIMING-MINIMUM System External Synchronization VIA Test BUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tchcl Minimum Complexity System Timing RequirementsTclcl Tclch Timing Responses Characteristics Waveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode Tchgx CharacteristicsTinvch NMI, Test Tgvch Tchsv TclmlTclmh Tryhsh Tchdth TrhavTCLCL-45 TCLCL-35 TCLCL-40 Tchdtl Maximum Mode Waveforms Maximum Mode Waveforms Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing REQUEST/GRANT Sequence Timing Maximum Mode only HOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set Summary Arithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1