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Intel 8086-2, 8086-1 Waveforms, Testing INPUT, Output Waveform Testing Load Circuit, Minimum Mode

Models: 8086 8086-2 8086-1

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8086

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

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A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 1.5V for both a Logic ‘‘1’’ and ‘‘0’’.

WAVEFORMS

MINIMUM MODE

231455 – 12

CL Includes Jig Capacitance

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Intel 8086-2, 8086-1 manual Waveforms, Testing INPUT, Output Waveform Testing Load Circuit, Minimum Mode

Contents

CPU Block Diagram Pin Configuration BHE LOW BHE/S Ready ResetIntr Test High LOWRQ/GT0 RQ/GT1 ALE IntaDT/R DEN Functional Description BUS Operation Minimum and Maximum Modes Minimum Mode 8086 Typical Configuration Write I/O Read I/OInstruction Fetch Read Data from Memory Alternate Data extra segment Processor Reset and InitializationAddressing Interrupt Operations READ/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt System TIMING-MINIMUM System External Synchronization VIA Test BUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclcl Minimum Complexity System Timing RequirementsTclch Tchcl Timing Responses Characteristics Waveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode Tinvch CharacteristicsNMI, Test Tgvch Tchgx Tclmh TclmlTryhsh Tchsv TCLCL-45 TCLCL-35 TCLCL-40 TrhavTchdtl Tchdth Maximum Mode Waveforms Maximum Mode BUS Lock Signal Timing Maximum Mode Only Reset Timing Asynchronous Signal RecognitionREQUEST/GRANT Sequence Timing Maximum Mode only Waveforms HOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set Summary Arithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1