Waveforms, Asynchronous Signal Recognition | Intel 8086-1, 8086-2

8086

WAVEFORMS (Continued)

ASYNCHRONOUS SIGNAL RECOGNITION

231455 – 17

NOTE:

1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)	RESET TIMING

231455 – 18

231455 – 19

REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

231455 – 20

NOTE:

The coprocessor may not drive the buses outside the region shown without risking contention.

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Image 24

Intel 8086-1, 8086-2 Waveforms, Asynchronous Signal Recognition, BUS Lock Signal Timing Maximum Mode Only Reset Timing

Contents

Pin Configuration CPU Block Diagram LOW BHE/S BHE Reset ReadyIntr Test LOW HighRQ/GT0 RQ/GT1 Inta ALEDT/R DEN Functional Description Minimum and Maximum Modes BUS Operation Minimum Mode 8086 Typical Configuration Read I/O Write I/OInstruction Fetch Read Data from Memory Processor Reset and Initialization Alternate Data extra segmentAddressing Interrupt Operations Maskable Interrupt Intr HaltREAD/MODIFY/WRITE Semaphore Operations VIA Lock External Synchronization VIA Test System TIMING-MINIMUM System BUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Minimum Complexity System Timing Requirements TclclTclch Tchcl Characteristics Timing Responses Testing INPUT, Output Waveform Testing Load Circuit Minimum ModeWaveforms Waveforms Minimum Mode Characteristics TinvchNMI, Test Tgvch Tchgx Tclml TclmhTryhsh Tchsv Trhav TCLCL-45 TCLCL-35 TCLCL-40Tchdtl Tchdth Maximum Mode Waveforms Maximum Mode Asynchronous Signal Recognition BUS Lock Signal Timing Maximum Mode Only Reset TimingREQUEST/GRANT Sequence Timing Maximum Mode only Waveforms HOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data Transfer Arithmetic Logic 8086 Data Sheet Revision Review 1 reg 1 1Bit w e Segment 000 001 010 011 100 101 110 111